| /external/vixl/src/aarch32/ |
| D | disasm-aarch32.h | 240 virtual DisassemblerStream& operator<<(DRegister reg) {
1326 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1332 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
1335 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1341 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
1343 void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm);
1350 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1356 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1362 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
1368 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
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| D | assembler-aarch32.h | 350 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
354 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
357 DRegister rd,
358 DRegister rm);
370 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
372 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
375 DRegister rd,
376 DRegister rn,
389 DRegister rd,
392 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
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| D | disasm-aarch32.cc | 3721 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vaba()
3735 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vabal()
3742 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vabd()
3764 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vabdl()
3772 DRegister rd, in vabs()
3773 DRegister rm) { in vabs()
3798 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vacge()
3820 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vacgt()
3842 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vacle()
3864 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vaclt()
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| D | macro-assembler-aarch32.h | 247 EmitLiteralCondDtDL(DataType dt, DRegister rt) : dt_(dt), rt_(rt) {} in EmitLiteralCondDtDL()
256 DRegister rt_;
817 void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) { in Vldr()
824 void Vldr(DataType dt, DRegister rd, RawLiteral* literal) { in Vldr()
827 void Vldr(Condition cond, DRegister rd, RawLiteral* literal) { in Vldr()
830 void Vldr(DRegister rd, RawLiteral* literal) { in Vldr()
893 void Vldr(Condition cond, DRegister rd, double v) { in Vldr()
902 void Vldr(DRegister rd, double v) { Vldr(al, rd, v); } in Vldr()
904 void Vmov(Condition cond, DRegister rt, double v) { Vmov(cond, F64, rt, v); } in Vmov()
905 void Vmov(DRegister rt, double v) { Vmov(al, F64, rt, v); } in Vmov()
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| D | instructions-aarch32.h | 174 class DRegister; variable
184 DRegister D() const;
218 class DRegister : public VRegister {
220 DRegister() : VRegister(kNoRegister, 0, kDRegSizeInBits) {} in DRegister() function
221 explicit DRegister(uint32_t code) in DRegister() function
244 inline std::ostream& operator<<(std::ostream& os, const DRegister reg) {
321 class DRegisterLane : public DRegister {
325 DRegisterLane(DRegister reg, uint32_t lane) in DRegisterLane()
326 : DRegister(reg.GetCode()), lane_(lane) {} in DRegisterLane()
327 DRegisterLane(uint32_t code, uint32_t lane) : DRegister(code), lane_(lane) {} in DRegisterLane()
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| D | instructions-aarch32.cc | 85 DRegister VRegister::D() const { in D()
87 return DRegister(GetCode()); in D()
140 DRegister VRegisterList::GetFirstAvailableDRegister() const { in GetFirstAvailableDRegister()
142 if (((list_ >> (i * 2)) & 0x3) == 0x3) return DRegister(i); in GetFirstAvailableDRegister()
144 return DRegister(); in GetFirstAvailableDRegister()
168 DRegister first = reglist.GetFirstDRegister(); in operator <<()
169 DRegister last = reglist.GetLastDRegister(); in operator <<()
178 DRegister first = nreglist.GetFirstDRegister(); in operator <<()
201 first = DRegister(next); in operator <<()
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| D | assembler-aarch32.cc | 4007 const DRegister& dreg = dreglist.GetFirstDRegister(); in fldmdbx()
4020 const DRegister& dreg = dreglist.GetFirstDRegister(); in fldmdbx()
4041 const DRegister& dreg = dreglist.GetFirstDRegister(); in fldmiax()
4054 const DRegister& dreg = dreglist.GetFirstDRegister(); in fldmiax()
4077 const DRegister& dreg = dreglist.GetFirstDRegister(); in fstmdbx()
4090 const DRegister& dreg = dreglist.GetFirstDRegister(); in fstmdbx()
4111 const DRegister& dreg = dreglist.GetFirstDRegister(); in fstmiax()
4124 const DRegister& dreg = dreglist.GetFirstDRegister(); in fstmiax()
12740 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vaba()
12800 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vabal()
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| D | macro-assembler-aarch32.cc | 135 DRegister UseScratchRegisterScope::AcquireD() { in AcquireD()
137 DRegister reg = in AcquireD()
917 Vpush(Untyped64, DRegisterList(DRegister(reg.GetCode()))); in PushRegister()
942 Vcvt(F64, F32, DRegister(*vfp_count), SRegister(*vfp_count * 2)); in PreparePrintfArgument()
948 Vpop(Untyped64, DRegisterList(DRegister(*vfp_count))); in PreparePrintfArgument()
1643 DRegister rd, in Delegate()
2464 DRegister rd, in Delegate()
2559 DRegister rd, in Delegate()
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| D | operands-aarch32.h | 478 DOperand(DRegister rm) // NOLINT(runtime/explicit) in DOperand()
481 DRegister GetRegister() const { in GetRegister()
483 return DRegister(rm_.GetCode()); in GetRegister()
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.h | 630 void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL);
632 void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL);
634 void vmovdr(DRegister dd, int i, Register rt, Condition cond = AL);
638 void vmovd(DRegister dd, DRegister dm, Condition cond = AL);
647 bool vmovd(DRegister dd, double d_imm, Condition cond = AL);
655 void vldrd(DRegister dd, Address ad, Condition cond = AL);
658 void vstrd(DRegister dd, Address ad, Condition cond = AL);
667 DRegister first, intptr_t count, Condition cond = AL);
669 DRegister first, intptr_t count, Condition cond = AL);
675 void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL);
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| D | assembler_arm.cc | 688 void Assembler::vmovdr(DRegister dn, int i, Register rt, Condition cond) {
706 void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2,
727 void Assembler::vmovrrd(Register rt, Register rt2, DRegister dm,
775 void Assembler::vldrd(DRegister dd, Address ad, Condition cond) {
788 void Assembler::vstrd(DRegister dd, Address ad, Condition cond) { in vstrd()
829 DRegister start, in EmitMultiVDMemOp()
867 DRegister first, intptr_t count, Condition cond) { in vldmd()
876 DRegister first, intptr_t count, Condition cond) { in vstmd()
905 DRegister dd, DRegister dn, DRegister dm) {
928 void Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceRegistersARM32.h | 65 enum DRegister { enum
195 static inline DRegister getEncodedDReg(RegNumT RegNum) { in getEncodedDReg()
197 return DRegister(RegTable[RegNum].Encoding); in getEncodedDReg()
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| /external/vixl/test/aarch32/ |
| D | test-utils-aarch32.cc | 73 DRegister rt(i); in Dump()
145 const DRegister& dreg) { in Equal64()
236 const DRegister& dreg) { in EqualFP64()
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| D | test-utils-aarch32.h | 177 const DRegister& dreg);
185 const DRegister& dreg);
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| D | test-assembler-aarch32.cc | 3308 VIXL_CHECK(masm.AliasesAvailableScratchRegister(DRegister(s / 2))); in TEST()
3319 if (temps.IsAvailable(DRegister(d))) { in TEST()
3320 VIXL_CHECK(masm.AliasesAvailableScratchRegister(DRegister(d))); in TEST()
3324 VIXL_CHECK(!masm.AliasesAvailableScratchRegister(DRegister(d))); in TEST()
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