| /external/llvm/test/CodeGen/Mips/ |
| D | fcopysign-f32-f64.ll | 41 ; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
47 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
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| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_64.c | 85 ins = (shift == 32) ? DSLL32 : DSLL; in load_immediate()
113 FAIL_IF(push_inst(compiler, DSLL | TA(dst_ar) | DA(dst_ar) | SH_IMM(shift - shift2), dst_ar)); in load_immediate()
115 FAIL_IF(push_inst(compiler, DSLL | TA(dst_ar) | DA(dst_ar) | SH_IMM(shift2), dst_ar)); in load_immediate()
239 …FAIL_IF(push_inst(compiler, SELECT_OP(DSLL, SLL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABL… in emit_single_op()
423 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV); in emit_single_op()
443 FAIL_IF(push_inst(compiler, DSLL | T(dst) | D(dst) | SH_IMM(16), DR(dst))); in emit_const()
445 FAIL_IF(push_inst(compiler, DSLL | T(dst) | D(dst) | SH_IMM(16), DR(dst))); in emit_const()
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| D | sljitNativeMIPS_common.c | 130 #define DSLL (HI(0) | LO(56)) macro
194 #define SLL_W DSLL
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | Mips64InstrInfo.td | 116 def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
198 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
200 def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
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| /external/valgrind/none/tests/mips64/ |
| D | shift_instructions.c | 6 DROTR=0, DROTR32, DROTRV, DSLL, enumerator
56 case DSLL: in main()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAnalyzeImmediate.cpp | 138 SLL = Mips::DSLL; in Analyze()
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| D | MipsLongBranch.cpp | 395 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64) in expandToLongBranch()
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| D | Mips64InstrInfo.td | 140 def DSLL : StdMMR6Rel, shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL,
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| D | MipsSEISelLowering.cpp | 3228 unsigned ShiftOp = Subtarget.isABI_N64() ? Mips::DSLL : Mips::SLL; in emitINSERT_DF_VIDX()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 455 DSLL = ((7U << 3) + 0), enumerator
964 FunctionFieldToBitNumber(DSLL) | FunctionFieldToBitNumber(DSLL32) |
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| D | disasm-mips64.cc | 1166 case DSLL: in DecodeTypeRegisterSPECIAL()
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| D | assembler-mips64.cc | 1856 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, DSLL); in dsll()
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| D | simulator-mips64.cc | 3575 case DSLL: in DecodeTypeRegisterSPECIAL()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 69 case Mips::DSLL: in LowerLargeShift()
196 case Mips::DSLL: in encodeInstruction()
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| D | MipsTargetStreamer.cpp | 207 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2237 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2266 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
2473 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
2476 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3629 FirstShift = Mips::DSLL; in expandDRotationImm()
3652 SecondShift = Mips::DSLL; in expandDRotationImm()
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