Searched refs:DefR (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 59 RegisterRef DefR = { Dst.getReg(), Dst.getSubReg() }; in interpretAsCopy() local
65 unsigned S = DFG.getTRI().composeSubRegIndices(DefR.Sub, I.SubIdx); in interpretAsCopy()
66 RegisterRef DR = { DefR.Reg, S }; in interpretAsCopy()
|
| D | HexagonGenMux.cpp | 73 unsigned DefR, PredR; member
79 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
299 BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR) in genMuxInBlock()
|
| D | HexagonBitSimplify.cpp | 1167 unsigned DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local
1168 if (!TargetRegisterInfo::isVirtualRegister(DefR)) in computeUsedBits()
1170 Pending.push_back(DefR); in computeUsedBits()
2331 unsigned DefR; member
2338 bool isBitShuffle(const MachineInstr *MI, unsigned DefR) const;
2339 bool isStoreInput(const MachineInstr *MI, unsigned DefR) const;
2357 DefR = HexagonLoopRescheduling::getDefReg(&P); in PhiInfo()
2395 unsigned DefR) const { in isBitShuffle()
2553 dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi(" in processLoop()
2581 unsigned DefR = Defs.find_first(); in processLoop() local
[all …]
|
| D | HexagonOptAddrMode.cpp | 80 bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
530 unsigned DefR = MI->getOperand(0).getReg(); in processBlock() local
535 if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc)) in processBlock()
558 if (op.isReg() && op.isUse() && DefR == op.getReg()) in processBlock()
|
| D | HexagonEarlyIfConv.cpp | 418 unsigned DefR = MI.getOperand(0).getReg(); in isValid() local
419 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in isValid()
957 unsigned DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
964 const TargetRegisterClass *RC = MRI->getRegClass(DefR); in eliminatePhis()
969 MRI->replaceRegWith(DefR, NewR); in eliminatePhis()
|