Home
last modified time | relevance | path

Searched refs:Defs (Results 1 – 25 of 191) sorted by relevance

12345678

/external/lzma/CPP/7zip/Archive/7z/
D7zItem.h92 CBoolVector Defs; member
97 Defs.ClearAndSetSize(newSize); in ClearAndSetSize()
103 Defs.Clear(); in Clear()
109 Defs.ReserveDown(); in ReserveDown()
113 bool ValidAndDefined(unsigned i) const { return i < Defs.Size() && Defs[i]; } in ValidAndDefined()
118 CBoolVector Defs; member
123 Defs.Clear(); in Clear()
129 Defs.ReserveDown(); in ReserveDown()
135 if (index < Defs.Size() && Defs[index]) in GetItem()
146 bool CheckSize(unsigned size) const { return Defs.Size() == size || Defs.Size() == 0; } in CheckSize()
D7zOut.cpp337 for (i = 0; i < digests.Defs.Size(); i++) in WriteHashDigests()
338 if (digests.Defs[i]) in WriteHashDigests()
344 if (numDefined == digests.Defs.Size()) in WriteHashDigests()
349 WriteBoolVector(digests.Defs); in WriteHashDigests()
351 for (i = 0; i < digests.Defs.Size(); i++) in WriteHashDigests()
352 if (digests.Defs[i]) in WriteHashDigests()
446 digests2.Defs.Add(digests.Defs[digestIndex]); in WriteSubStreamsInfo()
497 for (i = 0; i < v.Defs.Size(); i++) in WriteUInt64DefVector()
498 if (v.Defs[i]) in WriteUInt64DefVector()
504 WriteAlignedBoolHeader(v.Defs, numDefined, type, 8); in WriteUInt64DefVector()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp67 BitVector Defs, Uses; member
68 DefUseInfo() : Defs(), Uses() {} in DefUseInfo()
69 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
91 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
122 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
129 expandReg(*R++, Defs); in getDefsUses()
139 BitVector &Set = Mo->isDef() ? Defs : Uses; in getDefsUses()
149 BitVector Defs(NR), Uses(NR); in buildMaps() local
154 Defs.reset(); in buildMaps()
156 getDefsUses(MI, Defs, Uses); in buildMaps()
[all …]
DHexagonInstrInfoV3.td33 let Defs = !if (CSR, VolatileV3.Regs, []);
52 let Defs = !if (CSR, VolatileV3.Regs, []);
69 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
72 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [PC, R31, R6, R7, P0] in
85 let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
97 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in
198 let Defs = [USR_OVF], hasSideEffects = 0 in
227 let Defs = [USR_OVF], hasSideEffects = 0 in
270 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
DHexagonIsetDx.td32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBr…
42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicated…
122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBran…
180 let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = Double…
277 let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffect…
536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPr…
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
[all …]
DHexagonBitSimplify.cpp157 static void getInstrDefs(const MachineInstr &MI, RegisterSet &Defs);
224 RegisterSet Defs; in INITIALIZE_PASS_DEPENDENCY() local
226 getInstrDefs(I, Defs); in INITIALIZE_PASS_DEPENDENCY()
228 NewAVs.insert(Defs); in INITIALIZE_PASS_DEPENDENCY()
244 RegisterSet &Defs) { in getInstrDefs() argument
251 Defs.insert(R); in getInstrDefs()
1417 RegisterSet Defs; in processBlock() local
1422 Defs.clear(); in processBlock()
1423 HBS::getInstrDefs(*I, Defs); in processBlock()
1424 if (Defs.count() != 1) in processBlock()
[all …]
DHexagonExpandCondsets.cpp259 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
428 SetVector<MachineBasicBlock*> Defs; in updateDeadsInRange() local
429 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs, in updateDeadsInRange()
431 for (MachineBasicBlock *D : Defs) in updateDeadsInRange()
439 if (Defs.count(B)) in updateDeadsInRange()
459 Defs.insert(DefI->getParent()); in updateDeadsInRange()
479 if (Dominate(Defs, BB)) in updateDeadsInRange()
792 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs, in canMoveOver() argument
807 if (isRefInMap(RR, Defs, Exec_Then)) in canMoveOver()
977 ReferenceMap Uses, Defs; in predicate() local
[all …]
DHexagonRDFOpt.cpp242 NodeList Defs; in rewrite() local
247 Defs = DFG.getRelatedRefs(IA, DA); in rewrite()
248 if (!std::all_of(Defs.begin(), Defs.end(), IsDead)) in rewrite()
254 for (auto D : Defs) in rewrite()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb2ITBlockPass.cpp45 SmallSet<unsigned, 4> &Defs,
56 SmallSet<unsigned, 4> &Defs, in TrackDefUses() argument
85 Defs.insert(Reg); in TrackDefUses()
88 Defs.insert(*Subreg); in TrackDefUses()
109 SmallSet<unsigned, 4> &Defs, in MoveCopyOutOfITBlock() argument
124 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
166 SmallSet<unsigned, 4> Defs; in InsertITInstructions() local
179 Defs.clear(); in InsertITInstructions()
181 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
218 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCBoolRetToInt.cpp62 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
65 Defs.insert(V); in findAllDefs()
71 if (Defs.insert(Op).second) in findAllDefs()
74 return Defs; in findAllDefs()
196 auto Defs = findAllDefs(U); in runOnUse() local
199 if (!std::any_of(Defs.begin(), Defs.end(), isa<Instruction, Value *>)) in runOnUse()
205 for (Value *V : Defs) in runOnUse()
209 for (Value *V : Defs) in runOnUse()
220 for (Value *V : Defs) in runOnUse()
/external/llvm/lib/Target/Mips/
DMipsDSPInstrInfo.td91 class Defs<list<Register> Regs> {
92 list<Register> Defs = Regs;
547 Defs<[DSPOutFlag20]>;
551 IsCommutable, Defs<[DSPOutFlag20]>;
555 Defs<[DSPOutFlag20]>;
559 Defs<[DSPOutFlag20]>;
563 Defs<[DSPOutFlag20]>;
567 IsCommutable, Defs<[DSPOutFlag20]>;
571 Defs<[DSPOutFlag20]>;
575 Defs<[DSPOutFlag20]>;
[all …]
DMipsDelaySlotFiller.cpp118 BitVector Defs, Uses; member in __anone77742d70111::RegDefsUses
182 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anone77742d70111::MemDefsUses
320 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
329 Defs.set(Mips::RA); in init()
335 Defs.reset(Mips::AT); in init()
346 Defs.set(Mips::RA); in setCallerSaved()
347 Defs.set(Mips::RA_64); in setCallerSaved()
361 Defs |= CallerSavedRegs; in setCallerSaved()
374 Defs |= AllocSet.flip(); in setUnallocatableRegs()
397 Defs |= NewDefs; in update()
[all …]
DMicroMipsDSPInstrInfo.td190 "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
192 "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
194 "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
228 Defs<[DSPOutFlag22]>;
231 Defs<[DSPOutFlag22]>;
234 Defs<[DSPOutFlag22]>;
237 Defs<[DSPOutFlag22]>;
262 "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
265 Defs<[DSPOutFlag22]>;
267 "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
[all …]
/external/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp51 SmallSet<unsigned, 4> &Defs,
62 SmallSet<unsigned, 4> &Defs, in TrackDefUses() argument
92 Defs.insert(*Subreg); in TrackDefUses()
126 SmallSet<unsigned, 4> &Defs, in MoveCopyOutOfITBlock() argument
141 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
183 SmallSet<unsigned, 4> Defs; in InsertITInstructions() local
196 Defs.clear(); in InsertITInstructions()
198 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
239 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
249 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp39 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
40 Defs[Hexagon::LC0].insert(Unconditional); in init()
43 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
44 Defs[Hexagon::LC1].insert(Unconditional); in init()
112 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
156 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
169 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
334 if (!Defs.count(P) || LatePreds.count(P)) { in checkPredicates()
348 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
383 for (const auto& I : Defs) { in checkRegisters()
[all …]
/external/llvm/lib/CodeGen/
DLiveVariables.cpp444 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef() argument
483 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
487 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs() argument
488 while (!Defs.empty()) { in UpdatePhysRegDefs()
489 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
490 Defs.pop_back(); in UpdatePhysRegDefs()
501 SmallVectorImpl<unsigned> &Defs) { in runOnInstr() argument
561 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
563 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
568 SmallVector<unsigned, 4> Defs; in runOnBlock() local
[all …]
DMachineInstrBundle.cpp135 SmallVector<MachineOperand*, 4> Defs; in finalizeBundle() local
142 Defs.push_back(&MO); in finalizeBundle()
167 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in finalizeBundle()
168 MachineOperand &MO = *Defs[i]; in finalizeBundle()
195 Defs.clear(); in finalizeBundle()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrControl.td15 let Defs = [ARGUMENTS] in {
32 } // Defs = [ARGUMENTS]
39 let Defs = [ARGUMENTS] in {
64 let Uses = [EXPR_STACK], Defs = [EXPR_STACK] in {
69 } // Uses = [EXPR_STACK], Defs = [EXPR_STACK]
95 } // Defs = [ARGUMENTS]
DWebAssemblyInstrFloat.td15 let Defs = [ARGUMENTS] in {
39 } // Defs = [ARGUMENTS]
51 let Defs = [ARGUMENTS] in {
62 } // Defs = [ARGUMENTS]
78 let Defs = [ARGUMENTS] in {
87 } // Defs = [ARGUMENTS]
/external/lzma/C/
D7z.h64 Byte *Defs; /* MSB 0 bit numbering */ member
70 Byte *Defs; /* MSB 0 bit numbering */ member
77 #define SzBitWithVals_Check(p, i) ((p)->Defs && ((p)->Defs[(i) >> 3] & (0x80 >> ((i) & 7))) != 0)
/external/llvm/utils/TableGen/
DCTagsEmitter.cpp67 const auto &Defs = Records.getDefs(); in run() local
70 Tags.reserve(Classes.size() + Defs.size()); in run()
73 for (const auto &D : Defs) in run()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrArithmetic.td46 // AL is really implied by AX, but the registers in Defs must match the
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
70 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
80 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
85 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
89 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
95 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
[all …]
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td57 // AL is really implied by AX, but the registers in Defs must match the
60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
112 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveVariables.cpp423 SmallVector<unsigned, 4> &Defs) { in HandlePhysRegDef() argument
462 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
466 SmallVector<unsigned, 4> &Defs) { in UpdatePhysRegDefs() argument
467 while (!Defs.empty()) { in UpdatePhysRegDefs()
468 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
469 Defs.pop_back(); in UpdatePhysRegDefs()
510 SmallVector<unsigned, 4> Defs; in runOnMachineFunction() local
515 HandlePhysRegDef(*II, 0, Defs); in runOnMachineFunction()
568 HandlePhysRegDef(MOReg, MI, Defs); in runOnMachineFunction()
570 UpdatePhysRegDefs(MI, Defs); in runOnMachineFunction()
[all …]
/external/clang/utils/TableGen/
DNeonEmitter.cpp504 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
506 SmallVectorImpl<Intrinsic *> &Defs);
508 SmallVectorImpl<Intrinsic *> &Defs);
1966 SmallVectorImpl<Intrinsic *> &Defs) { in genBuiltinsDef() argument
1973 for (auto *Def : Defs) { in genBuiltinsDef()
1997 SmallVectorImpl<Intrinsic *> &Defs) { in genOverloadTypeCheckCode() argument
2011 for (auto *Def : Defs) { in genOverloadTypeCheckCode()
2093 SmallVectorImpl<Intrinsic *> &Defs) { in genIntrinsicRangeCheckCode() argument
2098 for (auto *Def : Defs) { in genIntrinsicRangeCheckCode()
2179 SmallVector<Intrinsic *, 128> Defs; in runHeader() local
[all …]

12345678