/external/llvm/lib/CodeGen/ |
D | RegisterCoalescer.h | 39 unsigned DstIdx; variable 61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair() 68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair() 106 unsigned getDstIdx() const { return DstIdx; } in getDstIdx()
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D | RegisterCoalescer.cpp | 315 SrcIdx = DstIdx = 0; in setRegisters() 362 SrcIdx, DstIdx); in setRegisters() 371 DstIdx = SrcSub; in setRegisters() 384 if (DstIdx && !SrcIdx) { in setRegisters() 386 std::swap(SrcIdx, DstIdx); in setRegisters() 405 std::swap(SrcIdx, DstIdx); in flip() 429 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); in isCoalescable() 444 TRI.composeSubRegIndices(DstIdx, DstSub); in isCoalescable() 887 unsigned DstIdx = CP.isFlipped() ? CP.getSrcIdx() : CP.getDstIdx(); in reMaterializeTrivialDef() local 927 if (SrcIdx && DstIdx) in reMaterializeTrivialDef() [all …]
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D | TwoAddressInstructionPass.cpp | 132 unsigned SrcIdx, unsigned DstIdx, 1211 unsigned SrcIdx, unsigned DstIdx, in tryInstructionTransform() argument 1217 unsigned regA = MI.getOperand(DstIdx).getReg(); in tryInstructionTransform() 1227 bool Commuted = tryInstructionCommute(&MI, DstIdx, SrcIdx, regBKilled, Dist); in tryInstructionTransform() 1409 unsigned DstIdx = 0; in collectTiedOperands() local 1410 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in collectTiedOperands() 1414 MachineOperand &DstMO = MI->getOperand(DstIdx); in collectTiedOperands() 1435 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx)); in collectTiedOperands() 1460 unsigned DstIdx = TiedPairs[tpi].second; in processTiedPairs() local 1462 const MachineOperand &DstMO = MI->getOperand(DstIdx); in processTiedPairs() [all …]
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | TwoAddressInstructionPass.cpp | 126 unsigned SrcIdx, unsigned DstIdx, 864 unsigned SrcIdx, unsigned DstIdx, unsigned Dist, in TryInstructionTransform() argument 867 unsigned regA = mi->getOperand(DstIdx).getReg(); in TryInstructionTransform() 876 if (!regBKilled && mi->getOperand(DstIdx).isDead() && in TryInstructionTransform() 1094 unsigned DstIdx = 0; in runOnMachineFunction() local 1095 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx)) in runOnMachineFunction() 1110 TiedOperands[regB].push_back(std::make_pair(SrcIdx, DstIdx)); in runOnMachineFunction() 1123 unsigned DstIdx = TiedPairs[0].second; in runOnMachineFunction() local 1127 mi->getOperand(DstIdx).getReg()) in runOnMachineFunction() 1130 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist, in runOnMachineFunction() [all …]
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D | VirtRegRewriter.cpp | 1489 unsigned &DstIdx) { in CommuteChangesDestination() argument 1502 DstIdx = 2; in CommuteChangesDestination()
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/external/llvm/lib/Target/AMDGPU/ |
D | R600ExpandSpecialInstrs.cpp | 83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in runOnMachineFunction() local 84 assert(DstIdx != -1); in runOnMachineFunction() 85 MachineOperand &DstOp = MI.getOperand(DstIdx); in runOnMachineFunction()
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D | R600Packetizer.cpp | 92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector() local 93 if (DstIdx == -1) { in getPreviousVector() 96 unsigned Dst = BI->getOperand(DstIdx).getReg(); in getPreviousVector()
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D | R600ISelLowering.cpp | 223 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); in EmitInstrWithCustomInserter() local 224 assert(DstIdx != -1); in EmitInstrWithCustomInserter() 228 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) || in EmitInstrWithCustomInserter()
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/external/llvm/lib/Analysis/ |
D | DependenceAnalysis.cpp | 3353 DstIdx = DstGEP->idx_begin(); in depends() local 3355 ++SrcIdx, ++DstIdx, ++P) { in depends() 3357 Pair[P].Dst = SE->getSCEV(*DstIdx); in depends() 3783 DstIdx = DstGEP->idx_begin(); in getSplitIteration() local 3785 ++SrcIdx, ++DstIdx, ++P) { in getSplitIteration() 3787 Pair[P].Dst = SE->getSCEV(*DstIdx); in getSplitIteration()
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/external/llvm/lib/Target/X86/ |
D | X86InstrInfo.cpp | 5691 unsigned DstIdx = (Imm >> 4) & 3; in foldMemoryOperandCustom() local 5697 unsigned NewImm = (DstIdx << 4) | ZMask; in foldMemoryOperandCustom()
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D | X86ISelLowering.cpp | 25817 unsigned DstIdx = (InsertPSMask >> 4) & 0x3; in combineTargetShuffle() local 25821 if (((ZeroMask | (1u << DstIdx)) == 0xF) && !Op0.isUndef()) in combineTargetShuffle() 25826 if ((ZeroMask & (1u << DstIdx)) && !Op1.isUndef()) in combineTargetShuffle() 25837 InsertPSMask |= (1u << DstIdx); in combineTargetShuffle() 25860 if ((InsertPSMask & (1u << i)) || (i == (int)DstIdx)) { in combineTargetShuffle()
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