Searched refs:DstMask (Results 1 – 5 of 5) sorted by relevance
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_dataflow.c | 469 unsigned int DstMask; member
626 unsigned int shared_mask = mask & d->DstMask; in get_readers_write_callback()
700 d->DstMask = dst_mask; in get_readers_for_single_write()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 1341 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore() local
1344 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask, in lowerPrivateTruncStore()
1346 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
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| /external/llvm/lib/CodeGen/ |
| D | RegisterCoalescer.cpp | 1175 LaneBitmask DstMask = TRI->getSubRegIndexLaneMask(DstSubIdx); in eliminateUndefCopy() local
1177 if ((SR.LaneMask & DstMask) == 0) in eliminateUndefCopy()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 4686 auto *DstMask = makeReg(IceType_i32); in lowerIntrinsicCall() local
4698 _and(DstMask, T6, T5); in lowerIntrinsicCall()
4702 _or(RegAt, RegAt, DstMask); in lowerIntrinsicCall()
4706 Context.insert<InstFakeUse>(DstMask); in lowerIntrinsicCall()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 1751 static bool isBitfieldDstMask(uint64_t DstMask, const APInt &BitsToBeInserted, in isBitfieldDstMask() argument
1757 APInt SignificantDstMask = APInt(BitWidth, DstMask); in isBitfieldDstMask()
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