Home
last modified time | relevance | path

Searched refs:DstR (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/Target/Hexagon/
DRDFCopy.cpp35 RegisterRef DstR = { Dst.getReg(), Dst.getSubReg() }; in interpretAsCopy() local
37 if (TargetRegisterInfo::isVirtualRegister(DstR.Reg)) { in interpretAsCopy()
41 if (MRI.getRegClass(DstR.Reg) != MRI.getRegClass(SrcR.Reg)) in interpretAsCopy()
43 } else if (TargetRegisterInfo::isPhysicalRegister(DstR.Reg)) { in interpretAsCopy()
47 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
54 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
DHexagonFrameLowering.cpp1380 unsigned DstR = MI->getOperand(0).getReg(); in expandCopy() local
1382 if (!Hexagon::ModRegsRegClass.contains(DstR) || in expandCopy()
1389 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR) in expandCopy()
1435 unsigned DstR = MI->getOperand(0).getReg(); in expandLoadInt() local
1451 BuildMI(B, It, DL, HII.get(TfrOpc), DstR) in expandLoadInt()
1507 unsigned DstR = MI->getOperand(0).getReg(); in expandLoadVecPred() local
1529 BuildMI(B, It, DL, HII.get(VandOpc), DstR) in expandLoadVecPred()
1603 unsigned DstR = MI->getOperand(0).getReg(); in expandLoadVec2() local
1604 unsigned DstHi = HRI.getSubReg(DstR, Hexagon::subreg_hireg); in expandLoadVec2()
1605 unsigned DstLo = HRI.getSubReg(DstR, Hexagon::subreg_loreg); in expandLoadVec2()
[all …]
DHexagonRDFOpt.cpp98 auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in interpretAsCopy() argument
99 EM.insert(std::make_pair(DstR, SrcR)); in interpretAsCopy()
DHexagonExpandCondsets.cpp250 MachineBasicBlock::iterator At, unsigned DstR,
613 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
628 .addReg(DstR, State, DstSR) in genCondTfrFor()
DHexagonGenInsert.cpp488 bool isValidInsertForm(unsigned DstR, unsigned SrcR, unsigned InsR,
637 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm() argument
639 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR); in isValidInsertForm()
DHexagonSplitDouble.cpp965 unsigned DstR = MI->getOperand(0).getReg(); in splitInstr() local
966 if (MRI->getRegClass(DstR) == DoubleRC) { in splitInstr()
/external/llvm/lib/Target/X86/
DX86FixupLEAs.cpp346 const unsigned DstR = MI.getOperand(0).getReg(); in processInstructionForSLM() local
349 if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR)) in processInstructionForSLM()
377 const MachineOperand &Src1 = MI.getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM()
378 const MachineOperand &Src2 = MI.getOperand(SrcR1 == DstR ? 3 : 1); in processInstructionForSLM()
388 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM()