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/external/valgrind/none/tests/x86/
Dbug152818-x86.stdout.exp1 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 4 (EAX = 123487FD, EFLAGS = …
2 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 3 (EAX = 123487FE, EFLAGS = …
3 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 2 (EAX = 123487FF, EFLAGS = …
4 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 1 (EAX = 123487AA, EFLAGS = …
5 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 0, count = 0 (EAX = 12348765, EFLAGS = …
6 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 0 (EAX = 12348765, EFLAGS = …
7 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 1 (EAX = 123487AA, EFLAGS = …
8 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 2 (EAX = 12348701, EFLAGS = …
9 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 3 (EAX = 12348702, EFLAGS = …
10 REP lodsb (EAX = 12348765, EFLAGS = ) => DF = 1, count = 4 (EAX = 12348703, EFLAGS = …
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrArithmetic.td48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
54 (implicit EFLAGS)]>; // AL,AH = AL*GR8
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
61 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
64 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/]>;
65 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
68 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/]>;
70 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
77 (implicit EFLAGS)]>; // AL,AH = AL*[mem8]
80 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
[all …]
DX86InstrCMovSetCC.td18 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
29 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))]>, TB;
34 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))]>, TB;
37 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst" in {
42 CondNode, EFLAGS))]>, TB, OpSize;
47 CondNode, EFLAGS))]>, TB;
52 CondNode, EFLAGS))]>, TB;
53 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
78 let Uses = [EFLAGS] in {
[all …]
DX86InstrCompiler.td44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
60 // sub / add which can clobber EFLAGS.
61 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
88 let Defs = [EFLAGS] in
95 (implicit EFLAGS)]>;
105 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
115 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP, EAX] in
122 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP, RAX] in
159 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
[all …]
DX86InstrInfo.td33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
736 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in
739 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in
768 let Defs = [EFLAGS] in {
771 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, TB, OpSize;
774 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, TB,
778 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, TB;
781 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, TB;
784 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, TB;
[all …]
DX86InstrControl.td51 let isBranch = 1, isTerminator = 1, Uses = [EFLAGS] in {
55 [(X86brcond bb:$dst, Cond, EFLAGS)]>, TB;
144 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
183 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
219 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
250 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
267 // __chkstk(MSVC): clobber R10, R11 and EFLAGS.
268 // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP.
269 let Defs = [RAX, R10, R11, RSP, EFLAGS],
283 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS],
DX86GenDAGISel.inc3372 /*7439*/ OPC_RecordChild2, // #4 = physreg input EFLAGS
3383 /*7461*/ OPC_EmitCopyToReg, 4, X86::EFLAGS,
3386 …edload>><<P:Predicate_load>>, (imm:i16)<<P:Predicate_i16immSExt8>>:$src, EFLAGS:i32), addr:iPTR:$d…
3391 /*7481*/ OPC_RecordChild2, // #4 = physreg input EFLAGS
3402 /*7503*/ OPC_EmitCopyToReg, 4, X86::EFLAGS,
3405 …edload>><<P:Predicate_load>>, (imm:i32)<<P:Predicate_i32immSExt8>>:$src, EFLAGS:i32), addr:iPTR:$d…
3410 /*7523*/ OPC_RecordChild2, // #4 = physreg input EFLAGS
3421 /*7545*/ OPC_EmitCopyToReg, 4, X86::EFLAGS,
3424 …edload>><<P:Predicate_load>>, (imm:i64)<<P:Predicate_i64immSExt8>>:$src, EFLAGS:i32), addr:iPTR:$d…
3429 /*7565*/ OPC_RecordChild2, // #4 = physreg input EFLAGS
[all …]
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
66 (implicit EFLAGS)], IIC_MUL8>, Sched<[WriteIMul]>;
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
76 [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
82 [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/],
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
92 (implicit EFLAGS)], IIC_MUL8>, SchedLoadReg<WriteIMulLd>;
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
[all …]
DX86InstrCMovSetCC.td18 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
30 (X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
36 (X86cmov GR64:$src1, GR64:$src2, CondNode, EFLAGS))],
40 let Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst",
46 CondNode, EFLAGS))], IIC_CMOV16_RM>,
52 CondNode, EFLAGS))], IIC_CMOV32_RM>,
58 CondNode, EFLAGS))], IIC_CMOV32_RM>, TB;
59 } // Uses = [EFLAGS], Predicates = [HasCMov], Constraints = "$src1 = $dst"
84 let Uses = [EFLAGS] in {
[all …]
DX86InstrCompiler.td44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS], Uses = [ESP] in {
63 // sub / add which can clobber EFLAGS.
64 let Defs = [RSP, EFLAGS], Uses = [RSP] in {
79 let usesCustomInserter = 1, Defs = [EFLAGS] in {
89 (implicit EFLAGS)]>;
93 let Defs = [EFLAGS] in
100 (implicit EFLAGS)]>;
108 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
115 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
[all …]
DX86InstrInfo.td33 // Unary and binary operator instructions that set EFLAGS as a side-effect.
43 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS
1155 let Defs = [ESP, EFLAGS], Uses = [ESP] in
1160 let Defs = [RSP, EFLAGS], Uses = [RSP] in
1166 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1174 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1213 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1216 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1248 let Defs = [EFLAGS] in {
1251 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
[all …]
DX86InstrTSX.td36 let Defs = [EFLAGS] in
38 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
DX86FixupSetCC.cpp105 if ((Op.getReg() == X86::EFLAGS) && (Op.isDef())) in findFlagsImpDef()
113 if ((Op.getReg() == X86::EFLAGS) && (Op.isUse())) in impUsesFlags()
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Duint64-to-float.ll28 ; %vreg7<def> = CMOV_FR32 %vreg6<kill>, %vreg5<kill>, 15, %EFLAGS<imp-use>; FR32:%vreg7,%vreg6,%v…
30 ; If the instruction had an EFLAGS<kill> flag, it wouldn't need to mark EFLAGS
Dpeep-test-2.ll4 ; EFLAGS value from the incl, however it can't be known whether the add
/external/llvm/test/CodeGen/X86/
Dhandle-move.ll11 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-u…
28 ; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-u…
61 ; Move EFLAGS dead def across another def:
62 ; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
63 ; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208…
Dremat-phys-dead.ll12 ; CHECK: Remat: %EAX<def,dead> = MOV32r0 %EFLAGS<imp-def,dead>, %AL<imp-def>
21 ; CHECK: Remat: %EAX<def> = MOV32r0 %EFLAGS<imp-def,dead>
Dpeephole-na-phys-copy-folding.ll8 ; EFLAGS. Make sure the flags are used directly, instead of needlessly using
127 ; cmpxchg sets EFLAGS, call clobbers it, then br uses EFLAGS.
158 ; Restore result of the first cmpxchg from D, put it back in EFLAGS.
164 ; Test from EFLAGS restored from first cmpxchg, jump if that fails.
Dclobber-fi0.ll6 ; In the code below we need to copy the EFLAGS because of scheduling constraints.
7 ; When copying the EFLAGS we need to write to the stack with push/pop. This forces
Di686-win-shrink-wrapping.ll8 ; Check that we do not use a basic block that has EFLAGS as live-in
18 ; this point, EFLAGS is live.
Dpeep-test-2.ll6 ; EFLAGS value from the incl, however it can't be known whether the add
D2012-01-16-mfence-nosse-flags.ll14 ; clobbers EFLAGS.
/external/strace/linux/x86_64/
Duserent.h19 { 8*EFLAGS, "8*EFL" },
/external/libunwind/src/x86/
Dunwind_i.h45 #define EFLAGS 9 macro
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h56 #define EFLAGS 144 macro

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