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Searched refs:EORS (Results 1 – 11 of 11) sorted by relevance

/external/llvm/test/MC/ARM/
Dthumb2-narrow-dp.ll193 EORS r0, r2, r1 // Must be wide - 3 distinct registers
194 EORS r5, r5, r1 // Should choose narrow
195 EORS r5, r1, r5 // Should choose narrow - commutative
196 EORS.W r0, r0, r1 // Explicitly wide
197 EORS.W r2, r1, r2
199 EORS r7, r7, r1 // Should use narrow
200 EORS r7, r1, r7 // Commutative
201 EORS r8, r1, r8 // high registers so must use wide encoding
202 EORS r8, r8, r1
203 EORS r6, r8, r6
[all …]
/external/vixl/test/aarch32/config/
Dcond-rd-rn-operand-rm-t32.json78 "Eors", // EORS{<q>} {<Rdn>}, <Rdn>, <Rm> ; T1
79 // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
Dcond-rd-rn-operand-const-a32.json41 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
Dcond-rd-rn-operand-const-t32.json47 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; T1
Dcond-rd-rn-operand-rm-shift-rs-a32.json38 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
Dcond-rd-rn-operand-rm-shift-amount-1to32-a32.json40 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
Dcond-rd-rn-operand-rm-shift-amount-1to31-a32.json40 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
Dcond-rd-rn-operand-rm-shift-amount-1to32-t32.json44 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
Dcond-rd-rn-operand-rm-shift-amount-1to31-t32.json44 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; T2
Dcond-rd-rn-operand-rm-a32.json49 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
/external/pcre/dist2/src/sljit/
DsljitNativeARM_T2_32.c114 #define EORS 0x4040 macro
768 return push_inst16(compiler, EORS | RD3(dst) | RN3(arg2)); in emit_op_imm()