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Searched refs:EXTRACT_SUBREG (Results 1 – 25 of 76) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsicsDerived.td20 (EXTRACT_SUBREG
22 (M2_dpmpyuu_s0 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
24 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
27 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
28 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))),
29 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)),
30 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg))),
32 (EXTRACT_SUBREG
35 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
36 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
DHexagonSelectCCInfo.td104 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
105 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
107 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
108 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
116 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_hireg),
117 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_hireg)),
120 (EXTRACT_SUBREG DoubleRegs:$tval, subreg_loreg),
121 (EXTRACT_SUBREG DoubleRegs:$fval, subreg_loreg)))>;
/external/llvm/test/CodeGen/AMDGPU/
Ddetect-dead-lanes.mir73 # CHECK: %5 = EXTRACT_SUBREG %0, {{[0-9]+}}
74 # CHECK: %6 = EXTRACT_SUBREG %5, {{[0-9]+}}
75 # CHECK: %7 = EXTRACT_SUBREG %5, {{[0-9]+}}
81 # CHECK: %9 = EXTRACT_SUBREG undef %8, {{[0-9]+}}
84 # CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}}
119 %5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
120 %6 = EXTRACT_SUBREG %5, %subreg.sub0
121 %7 = EXTRACT_SUBREG %5, %subreg.sub1
127 %9 = EXTRACT_SUBREG %8, %subreg.sub1
130 %10 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrCompiler.td1062 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1077 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1083 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1206 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1214 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1221 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1224 (MOVZX32rr8 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src1,
1230 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG
1237 (MOVZX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1240 (MOVZX64rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit)))>;
[all …]
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td268 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
269 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
286 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
287 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
1274 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1291 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1297 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1424 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1432 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1444 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
[all …]
DX86InstrAVX512.td722 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
724 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
726 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
728 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
730 (v8i16 (EXTRACT_SUBREG (v32i16 VR512:$src), sub_xmm))>;
732 (v16i8 (EXTRACT_SUBREG (v64i8 VR512:$src), sub_xmm))>;
737 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
739 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
741 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
743 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
[all …]
/external/llvm/test/CodeGen/MIR/X86/
Dsubregister-index-operands.mir16 # CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}}
28 %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td293 (STXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
295 (STXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
297 (STXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
309 (STXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
311 (STXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
313 (STXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
339 (STLXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
341 (STLXRH (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
343 (STLXRW (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
355 (STLXRB (EXTRACT_SUBREG GPR64:$val, sub_32), GPR64sp:$addr)>;
[all …]
DAArch64InstrInfo.td757 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
765 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
774 (SMADDLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
783 (SMSUBLrrr (i32 (EXTRACT_SUBREG GPR64:$Rn, sub_32)),
2020 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
2025 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
2082 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2087 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2191 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2194 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZPatterns.td16 (insn (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
27 (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
36 (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_l32))>;
74 (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), mode:$XBD2)>;
89 (insn (EXTRACT_SUBREG GR64:$R1, subreg_l32), pcrel32:$XBD2)> {
106 (insn (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
111 (insninv (EXTRACT_SUBREG GR64:$new, subreg_l32), mode:$addr,
DSystemZInstrFP.td87 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
96 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
104 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),
106 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
108 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
109 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
169 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hr32)>;
171 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
/external/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td850 (f64 (EXTRACT_SUBREG $S, sub_64))>;
852 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
861 (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
863 (f64 (EXTRACT_SUBREG $S, sub_64))>;
1317 (EXTRACT_SUBREG
1321 (EXTRACT_SUBREG
1325 dag LE_WORD_0 = (MFVSRWZ (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64));
1326 dag LE_WORD_1 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 1), sub_64));
1327 dag LE_WORD_2 = (MFVSRWZ (EXTRACT_SUBREG
1329 dag LE_WORD_3 = (MFVSRWZ (EXTRACT_SUBREG (XXSLDWI $S, $S, 3), sub_64));
[all …]
DPPCInstrInfo.td3056 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3065 (EXTRACT_SUBREG (rfrag8 $s1), sub_32)>;
3154 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
3156 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_lt)>;
3158 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_gt)>;
3160 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_gt)>;
3162 (EXTRACT_SUBREG (CMPWI $s1, imm:$imm), sub_eq)>;
3164 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_eq)>;
3178 (EXTRACT_SUBREG (CMPLWI (XORIS $s1, (HI16 imm:$imm)),
3182 (EXTRACT_SUBREG (CMPLWI $s1, imm:$imm), sub_lt)>;
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetOpcodes.h41 EXTRACT_SUBREG = 6, enumerator
/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp149 case TargetOpcode::EXTRACT_SUBREG: in lowersToCopies()
179 case TargetOpcode::EXTRACT_SUBREG: { in isCrossCopy()
267 case TargetOpcode::EXTRACT_SUBREG: { in transferUsedLanes()
336 case TargetOpcode::EXTRACT_SUBREG: { in transferDefinedLanes()
DExpandPostRAPseudos.cpp220 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinInstrInfo.td304 (EXTRACT_SUBREG (LOAD32p_8z P:$ptr), lo16)>;
306 (EXTRACT_SUBREG (LOAD32p_8z P:$ptr), lo16)>;
315 (EXTRACT_SUBREG (LOAD32p_imm16_8z P:$ptr, imm:$off),
318 (EXTRACT_SUBREG (LOAD32p_imm16_8z P:$ptr, imm:$off),
326 (EXTRACT_SUBREG (LOAD32p_8s P:$ptr), lo16)>;
333 (EXTRACT_SUBREG (LOAD32p_imm16_8s P:$ptr, imm:$off),
470 (STORE16pi (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$val, D)),
474 (STORE16pi (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS D:$val, D)),
516 (EXTRACT_SUBREG (MOVEsext8
523 (MOVEsext (EXTRACT_SUBREG D:$src, lo16))>;
[all …]
DREADME.txt124 D16L = EXTRACT_SUBREG D16, bfin_subreg_lo16
125 P16L = EXTRACT_SUBREG P16, bfin_subreg_lo16
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4202 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4208 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4214 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4240 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4247 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4262 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4269 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4331 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4339 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4348 (v2f32 (EXTRACT_SUBREG QPR:$src3,
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp657 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in Select()
671 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in Select()
742 SDNode *Div = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in Select()
755 SDNode *Rem = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, in Select()
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td2299 (EXTRACT_SUBREG
2311 (EXTRACT_SUBREG
2323 (EXTRACT_SUBREG
2335 (EXTRACT_SUBREG
2597 (EXTRACT_SUBREG
2936 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2938 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2956 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
2958 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1),
2966 (i32 (EXTRACT_SUBREG f64:$src, sub0)),
[all …]
DAMDGPUInstructions.td514 (EXTRACT_SUBREG $src, sub_reg)
567 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
569 (i32 (EXTRACT_SUBREG $src0, sub1)),
570 (i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td3756 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3761 (SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3766 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3771 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3777 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
3782 (SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
3787 (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
3792 (COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
3798 (f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
3802 (f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
[all …]
DMips64InstrInfo.td557 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
569 (EXTRACT_SUBREG GPR64:$src, sub_32)>;
571 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>;
575 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
577 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
579 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
582 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>;
/external/llvm/include/llvm/Target/
DTargetOpcodes.def41 /// EXTRACT_SUBREG - This instruction takes two operands: a register
45 HANDLE_TARGET_OPCODE(EXTRACT_SUBREG, 6)

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