Searched refs:Elt0 (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1184 SDValue Elt0 = OutVals[OIdx++]; in LowerCall() local
1187 Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0); in LowerCall()
1194 DAG.getConstant(0, dl, MVT::i32), Elt0, in LowerCall()
2243 SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, in LowerFormalArguments() local
2249 Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0); in LowerFormalArguments()
2253 InVals.push_back(Elt0); in LowerFormalArguments()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 2361 SDValue Elt0 = DAG.getConstant(0, MVT::i32); in LowerCTPOP() local
2366 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0); in LowerCTPOP()
2376 SDValue Elt0 = DAG.getConstant(0, MVT::i16); in LowerCTPOP() local
2386 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0); in LowerCTPOP()
2409 SDValue Elt0 = DAG.getConstant(0, MVT::i32); in LowerCTPOP() local
2420 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0); in LowerCTPOP()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5774 int Elt0 = MaskVals[i*2]; in LowerVECTOR_SHUFFLEv16i8() local
5778 if (Elt0 < 0 && Elt1 < 0) in LowerVECTOR_SHUFFLEv16i8()
5782 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) in LowerVECTOR_SHUFFLEv16i8()
5784 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) in LowerVECTOR_SHUFFLEv16i8()
5787 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; in LowerVECTOR_SHUFFLEv16i8()
5793 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { in LowerVECTOR_SHUFFLEv16i8()
5811 else if (Elt0 >= 0) in LowerVECTOR_SHUFFLEv16i8()
5819 if (Elt0 >= 0) { in LowerVECTOR_SHUFFLEv16i8()
5821 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); in LowerVECTOR_SHUFFLEv16i8()
5822 if ((Elt0 & 1) != 0) in LowerVECTOR_SHUFFLEv16i8()
|
| /external/llvm/test/CodeGen/X86/ |
| D | masked_gather_scatter.ll | 184 ; SCALAR-NEXT: %Elt0 = extractelement <16 x i32> %val, i32 0
186 ; SCALAR-NEXT: store i32 %Elt0, i32* %Ptr0, align 4
234 ; SCALAR: store i32 %Elt0, i32* %Ptr01, align 4
|