| /external/spirv-llvm/lib/SPIRV/ |
| D | OCLUtil.cpp | 164 unsigned ExtOp = ~0U; in getSPIRVInst() local
168 else if ((ExtOp = getExtOp(Info.MangledName, Info.UniqName)) != ~0U) in getSPIRVInst()
170 SPIRVEntry::create_unique(SPIRVEIS_OpenCL, ExtOp).get()); in getSPIRVInst()
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| D | SPIRVWriter.cpp | 344 SPIRVWord *ExtOp, in isBuiltinTransToExtInst() argument
373 if (ExtOp) in isBuiltinTransToExtInst()
374 *ExtOp = EOC; in isBuiltinTransToExtInst()
1196 SPIRVWord ExtOp = SPIRVWORD_MAX; in transCallInst() local
1232 &ExtOp, &Dec)) in transCallInst()
1236 ExtOp, in transCallInst()
1237 transArguments(CI, BB, SPIRVEntry::create_unique(ExtSetKind, ExtOp).get()), in transCallInst()
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| D | OCL20ToSPIRV.cpp | 958 unsigned ExtOp = ~0U; in transBuiltin() local
963 else if ((ExtOp = getExtOp(Info.MangledName, Info.UniqName)) != ~0U) in transBuiltin()
964 Info.UniqName = getSPIRVExtFuncName(SPIRVEIS_OpenCL, ExtOp); in transBuiltin()
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| D | SPIRVUtil.cpp | 410 getSPIRVExtFuncName(SPIRVExtInstSetKind Set, unsigned ExtOp, in getSPIRVExtFuncName() argument
419 ExtOpName = getName(static_cast<OCLExtOpKind>(ExtOp)); in getSPIRVExtFuncName()
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| D | SPIRVInternal.h | 601 std::string getSPIRVExtFuncName(SPIRVExtInstSetKind Set, unsigned ExtOp,
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| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| D | SPIRVInstruction.h | 1201 ExtOp(TheEntryPoint) {
1210 ExtOp(TheEntryPoint) {
1216 :ExtSetId(SPIRVWORD_MAX), ExtOp(ExtOC), ExtSetKind(SetKind) {}
1218 void setExtOp(unsigned ExtOC) { ExtOp = ExtOC;}
1223 return ExtOp;
1238 getEncoder(O) << ExtOp;
1251 getDecoder(I) >> ExtOp;
1257 validateBuiltin(ExtSetId, ExtOp);
1262 auto EOC = static_cast<OCLExtOpKind>(ExtOp);
1279 SPIRVWord ExtOp;
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| D | SPIRVEntry.cpp | 102 unsigned ExtOp) { in create_unique() argument
103 return std::unique_ptr<SPIRVExtInst>(new SPIRVExtInst(Set, ExtOp)); in create_unique()
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| D | SPIRVEntry.h | 309 unsigned ExtOp);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 4095 unsigned ExtOp, TruncOp; in PromoteNode() local
4097 ExtOp = ISD::BITCAST; in PromoteNode()
4101 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4105 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
4106 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
4113 unsigned ExtOp, TruncOp; in PromoteNode() local
4116 ExtOp = ISD::BITCAST; in PromoteNode()
4119 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
4122 ExtOp = ISD::FP_EXTEND; in PromoteNode()
4127 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
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| D | DAGCombiner.cpp | 9104 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND in FoldIntToFPToInt() local
9106 return DAG.getNode(ExtOp, SDLoc(N), VT, Src); in FoldIntToFPToInt()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 5834 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5837 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5841 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5843 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5846 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5848 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5851 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5877 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5879 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5881 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
[all …]
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| D | X86ISelLowering.cpp | 12539 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT, in InsertBitToMaskVector() local
12542 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp); in InsertBitToMaskVector()
14617 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op); in EmitTest() local
14618 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp, in EmitTest()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 3883 unsigned ExtOp, TruncOp; in PromoteNode() local
3885 ExtOp = ISD::BITCAST; in PromoteNode()
3889 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
3893 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); in PromoteNode()
3894 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
3901 unsigned ExtOp, TruncOp; in PromoteNode() local
3903 ExtOp = ISD::BITCAST; in PromoteNode()
3906 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
3909 ExtOp = ISD::FP_EXTEND; in PromoteNode()
3914 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); in PromoteNode()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2209 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2215 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2298 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2303 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2304 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2311 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2316 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2355 SDNode OpNode, SDNode ExtOp, bit Commutable>
2360 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2846 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 2916 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2922 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3006 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
3011 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3012 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3019 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
3024 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3073 SDNode OpNode, SDNode ExtOp, bit Commutable>
3078 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3584 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
[all …]
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| D | ARMISelLowering.cpp | 8806 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE; in AddCombineToVPADDL() local
8807 return DAG.getNode(ExtOp, dl, VT, tmp); in AddCombineToVPADDL()
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | IndVarSimplify.cpp | 1244 Value *ExtOp = createExtendInst(Op, WideType, Cmp->isSigned(), Cmp); in widenLoopCompare() local
1245 DU.NarrowUse->replaceUsesOfWith(Op, ExtOp); in widenLoopCompare()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 2186 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments() local
2188 p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr, in LowerFormalArguments()
2312 ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ? in LowerFormalArguments() local
2315 ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue), in LowerFormalArguments()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3162 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
3163 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 3782 Value *ExtOp, Value *IndexOp, in packTBLDVectorList() argument
3786 if (ExtOp) in packTBLDVectorList()
3787 TblOps.push_back(ExtOp); in packTBLDVectorList()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 5201 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_64SVR4() local
5202 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
5769 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerCall_Darwin() local
5770 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_Darwin()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5680 SDValue ExtOp = (EltIdx < 8) in LowerVECTOR_SHUFFLEv8i16() local
5685 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, in LowerVECTOR_SHUFFLEv8i16()
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