| /external/llvm/test/Transforms/InstCombine/ |
| D | pow-1.ll | 86 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]]) [[NUW_RO]]
88 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
166 ; CHECK-NEXT: [[FABS:%[a-z0-9]+]] = call double @fabs(double [[SQRT]])
168 ; CHECK-NEXT: [[SELECT:%[a-z0-9]+]] = select i1 [[FCMP]], double 0x7FF0000000000000, double [[FABS]]
|
| /external/llvm/test/CodeGen/X86/ |
| D | fnabs.ll | 4 ; FNABS(x) operation -> FNEG (FABS(x)).
5 ; If the FABS() result isn't used, the AND instruction should be eliminated.
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 450 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 524 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, enumerator
|
| D | BasicTTIImpl.h | 766 ISDs.push_back(ISD::FABS); in getIntrinsicInstrCost()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1010 if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps()) { in SelectBitOp()
1016 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1053 if (Opc != ISD::FABS && Opc != ISD::FNEG) { in SelectBitOp()
1073 case ISD::FABS: in SelectBitOp()
1124 if (Opc != ISD::FABS && Opc != ISD::FNEG) in SelectBitOp()
1231 case ISD::FABS: in Select()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 173 case ISD::FABS: in LegalizeOp()
|
| D | DAGCombiner.cpp | 1100 case ISD::FABS: return visitFABS(N); in visit()
5020 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && in visitBITCAST()
5030 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
5422 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) in visitFCOPYSIGN()
5423 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFCOPYSIGN()
5427 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); in visitFCOPYSIGN()
5434 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
5440 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
5441 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFCOPYSIGN()
5663 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); in visitFABS()
[all …]
|
| D | LegalizeFloatTypes.cpp | 66 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
849 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
902 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
|
| D | LegalizeVectorTypes.cpp | 71 case ISD::FABS: in ScalarizeVectorResult()
447 case ISD::FABS: in SplitVectorResult()
1298 case ISD::FABS: in WidenVectorResult()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 76 case ISD::FABS: R = SoftenFloatRes_FABS(N, ResNo); break; in SoftenFloatResult()
801 case ISD::FABS: in CanSkipSoftenFloatOperand()
816 case ISD::FABS: in CanSkipSoftenFloatOperand()
1016 case ISD::FABS: ExpandFloatRes_FABS(N, Lo, Hi); break; in ExpandFloatResult()
1076 Hi = DAG.getNode(ISD::FABS, dl, Tmp.getValueType(), Tmp); in ExpandFloatRes_FABS()
1869 case ISD::FABS: in PromoteFloatResult()
|
| D | SelectionDAGDumper.cpp | 152 case ISD::FABS: return "fabs"; in getOperationName()
|
| D | DAGCombiner.cpp | 1420 case ISD::FABS: return visitFABS(N); in visit()
7363 FPOpcode = ISD::FABS; in foldBitcastedFPLogic()
7467 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) && in visitBITCAST()
7483 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
7501 assert(N0.getOpcode() == ISD::FABS); in visitBITCAST()
8944 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) in visitFCOPYSIGN()
8945 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); in visitFCOPYSIGN()
8949 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0)); in visitFCOPYSIGN()
8956 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || in visitFCOPYSIGN()
8962 if (N1.getOpcode() == ISD::FABS) in visitFCOPYSIGN()
[all …]
|
| D | LegalizeVectorOps.cpp | 302 case ISD::FABS: in LegalizeOp()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 455 class FABS <RegisterClass rc> : AMDGPUShaderInst <
458 "FABS $dst, $src0",
|
| D | AMDGPUISelLowering.cpp | 242 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
407 setOperationAction(ISD::FABS, VT, Expand); in AMDGPUTargetLowering()
1299 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr); in LowerDIVREM24()
1302 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb); in LowerDIVREM24()
1707 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src); in LowerFRINT()
1737 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff); in LowerFROUND32()
|
| D | SIISelLowering.cpp | 2168 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS); in LowerFDIV32()
2539 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X) in performAndCombine()
2842 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) { in performSetCCCombine()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1663 setOperationAction(ISD::FABS, MVT::f64, Custom); in SparcTargetLowering()
1752 setOperationAction(ISD::FABS, MVT::f128, Legal); in SparcTargetLowering()
1755 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
1774 setOperationAction(ISD::FABS, MVT::f128, Custom); in SparcTargetLowering()
2704 assert(opcode == ISD::FNEG || opcode == ISD::FABS); in LowerF64Op()
2864 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) in LowerFNEGorFABS()
3073 case ISD::FABS: in LowerOperation()
|
| /external/v8/src/ppc/ |
| D | disasm-ppc.cc | 1024 case FABS: { in DecodeExt4()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrFPU.td | 155 defm FABS : FFR1P_M<0x5, "abs", fabs>;
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1065 FABS = FABS_s, enumerator
|
| D | disasm-arm64.cc | 999 FORMAT(FABS, "fabs"); in VisitFPDataProcessing1Source()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_64.c | 82 #define FABS 0x1e60c000 macro
1709 FAIL_IF(push_inst(compiler, (FABS ^ inv_bits) | VD(dst_r) | VN(src))); in sljit_emit_fop1()
|
| D | sljitNativePPC_common.c | 164 #define FABS (HI(63) | LO(264)) macro
1922 FAIL_IF(push_inst(compiler, FABS | FD(dst_r) | FB(src))); in sljit_emit_fop1()
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelDAGToDAG.cpp | 830 } else if (Opc == ISD::FABS) { in Select()
|