Searched refs:FGR64RegClass (Results 1 – 7 of 7) sorted by relevance
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); in MipsRegInfoRecord()67 const MCRegisterClass *FGR64RegClass; variable
193 for (RegIter Reg = Mips::FGR64RegClass.begin(), in getReservedRegs()194 EReg = Mips::FGR64RegClass.end(); Reg != EReg; ++Reg) in getReservedRegs()
143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()152 else if (Mips::FGR64RegClass.contains(SrcReg)) in copyPhysReg()160 else if (Mips::FGR64RegClass.contains(DestReg)) in copyPhysReg()208 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()281 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()
295 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandBuildPairF64()357 FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in expandExtractElementF64()455 } else if (Mips::FGR64RegClass.contains(Reg)) { in emitPrologue()
1646 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID); in emitSEL_D() local1648 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass); in emitSEL_D()3538 return std::make_pair(0U, &Mips::FGR64RegClass); in getRegForInlineAsmConstraint()
108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); in MipsSETargetLowering()
86 FGR64RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()