| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 259 X86_INTRINSIC_DATA(avx_min_pd_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
260 X86_INTRINSIC_DATA(avx_min_ps_256, INTR_TYPE_2OP, X86ISD::FMIN, 0),
796 X86_INTRINSIC_DATA(avx512_mask_min_pd_128, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
797 X86_INTRINSIC_DATA(avx512_mask_min_pd_256, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
798 X86_INTRINSIC_DATA(avx512_mask_min_pd_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
800 X86_INTRINSIC_DATA(avx512_mask_min_ps_128, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
801 X86_INTRINSIC_DATA(avx512_mask_min_ps_256, INTR_TYPE_2OP_MASK, X86ISD::FMIN, 0),
802 X86_INTRINSIC_DATA(avx512_mask_min_ps_512, INTR_TYPE_2OP_MASK, X86ISD::FMIN,
805 X86ISD::FMIN, X86ISD::FMIN_RND),
807 X86ISD::FMIN, X86ISD::FMIN_RND),
[all …]
|
| D | X86ISelLowering.h | 244 FMAX, FMIN, enumerator
|
| D | X86InstrFragmentsSIMD.td | 44 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
47 // Commutative and Associative FMIN and FMAX.
|
| D | README-SSE.txt | 332 specified. We should turn int_x86_sse_max_ss and X86ISD::FMIN etc. into other
|
| D | X86ISelLowering.cpp | 21838 case X86ISD::FMIN: in ReplaceNodeResults()
22139 case X86ISD::FMIN: return "X86ISD::FMIN"; in getTargetNodeName()
26473 Opcode = X86ISD::FMIN; in combineSelect()
26481 Opcode = X86ISD::FMIN; in combineSelect()
26490 Opcode = X86ISD::FMIN; in combineSelect()
26538 Opcode = X86ISD::FMIN; in combineSelect()
26545 Opcode = X86ISD::FMIN; in combineSelect()
26554 Opcode = X86ISD::FMIN; in combineSelect()
29821 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX); in combineFMinFMax()
29832 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break; in combineFMinFMax()
[all …]
|
| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu.h | 196 A_ALU2(FMIN)
|
| D | vc4_qpu_emit.c | 256 A(FMIN), in vc4_generate_code_block()
|
| D | vc4_qir.h | 716 QIR_ALU2(FMIN) in QIR_ALU1()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedA57.td | 462 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
464 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
466 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
468 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
470 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
|
| D | AArch64InstrInfo.td | 2612 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
2959 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>;
|
| /external/v8/src/arm64/ |
| D | constants-arm64.h | 1117 FMIN = FPDataProcessing2SourceFixed | 0x00005000, enumerator
1118 FMIN_s = FMIN,
1119 FMIN_d = FMIN | FP64,
|
| D | disasm-arm64.cc | 1031 FORMAT(FMIN, "fmin"); in VisitFPDataProcessing2Source()
|
| D | assembler-arm64.cc | 1935 FPDataProcessing2Source(fd, fn, fm, FMIN); in fmin()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 177 FMIN, enumerator
|
| D | ARMISelLowering.cpp | 917 case ARMISD::FMIN: return "ARMISD::FMIN"; in getTargetNodeName()
7830 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; in PerformSELECT_CCCombine()
7852 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; in PerformSELECT_CCCombine()
|
| D | ARMInstrNEON.td | 150 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 1213 FMIN = FPDataProcessing2SourceFixed | 0x00005000, enumerator
1214 FMIN_s = FMIN,
1215 FMIN_d = FMIN | FP64,
|
| D | disasm-aarch64.cc | 1517 FORMAT(FMIN, "fmin"); in VisitFPDataProcessing2Source()
|
| D | assembler-aarch64.cc | 2725 V(fmin, NEON_FMIN, FMIN) \
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.h | 196 FMAX, FMIN, enumerator
|
| D | X86InstrFragmentsSIMD.td | 41 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
|
| D | README-SSE.txt | 362 specified. We should turn int_x86_sse_max_ss and X86ISD::FMIN etc. into other
|
| D | X86ISelLowering.cpp | 10665 case X86ISD::FMIN: return "X86ISD::FMIN"; in getTargetNodeName()
12668 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
12676 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
12685 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
12733 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
12740 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
12749 Opcode = X86ISD::FMIN; in PerformSELECTCombine()
|
| D | X86GenFastISel.inc | 2709 // FastEmit functions for X86ISD::FMIN.
3690 case X86ISD::FMIN: return FastEmit_X86ISD_FMIN_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 2151 ### FMIN ### subsection
|