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Searched refs:FPSCR (Results 1 – 25 of 30) sorted by relevance

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/external/valgrind/none/tests/arm/
Dvfp.stdout.exp726 vcmp.f64 d0, d19 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 Dm 0xc004fef9 db22d0e5
727 vcmp.f64 d11, d16 :: FPSCR 0x20000000 Dd 0x40d6ecdc cccccccd Dm 0x40aac300 00000000
728 vcmp.f64 d21, d30 :: FPSCR 0x20000000 Dd 0xc0b1ac80 00000000 Dm 0xc11b9be6 00000000
729 vcmp.f64 d7, d28 :: FPSCR 0x20000000 Dd 0x407a9800 00000000 Dm 0xc07c84cc cccccccd
730 vcmp.f64 d29, d3 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 Dm 0x40e0e04e 66666666
731 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40000000 00000000 Dm 0x40000000 00000000
732 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40280bc6 a7ef9db2 Dm 0x40280bc6 a7ef9db2
733 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x00000000 00000000 Dm 0x00000000 00000000
734 vcmp.f64 d9, d2 :: FPSCR 0x60000000 Dd 0x7ff00000 00000000 Dm 0x7ff00000 00000000
735 vcmp.f64 d30, d15 :: FPSCR 0x60000000 Dd 0xfff00000 00000000 Dm 0xfff00000 00000000
[all …]
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Dvmrs.ll1 ; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
32 ; ASM: vmrs APSR_nzcv, FPSCR
/external/valgrind/none/tests/ppc32/
Dtest_dfp1.stdout.exp571 Test move to/from FPSCR
572 FPSCR binary floating point rounding mode 0000000000000000 == 0000000000000000? yes
573 FPSCR binary floating point rounding mode 0000000000000001 == 0000000000000001? yes
574 FPSCR binary floating point rounding mode 0000000000000002 == 0000000000000002? yes
575 FPSCR binary floating point rounding mode 0000000000000003 == 0000000000000003? yes
576 FPSCR decimal floating point rounding mode 0000000000000003 == 0000000000000003? yes
577 FPSCR decimal floating point rounding mode 0000000100000003 == 0000000100000003? yes
578 FPSCR decimal floating point rounding mode 0000000200000003 == 0000000200000003? yes
579 FPSCR decimal floating point rounding mode 0000000300000003 == 0000000300000003? yes
580 FPSCR decimal floating point rounding mode 0000000400000003 == 0000000400000003? yes
[all …]
/external/valgrind/none/tests/ppc64/
Dtest_dfp1.stdout.exp571 Test move to/from FPSCR
572 FPSCR binary floating point rounding mode 0000000000000000 == 0000000000000000? yes
573 FPSCR binary floating point rounding mode 0000000000000001 == 0000000000000001? yes
574 FPSCR binary floating point rounding mode 0000000000000002 == 0000000000000002? yes
575 FPSCR binary floating point rounding mode 0000000000000003 == 0000000000000003? yes
576 FPSCR decimal floating point rounding mode 0000000000000003 == 0000000000000003? yes
577 FPSCR decimal floating point rounding mode 0000000100000003 == 0000000100000003? yes
578 FPSCR decimal floating point rounding mode 0000000200000003 == 0000000200000003? yes
579 FPSCR decimal floating point rounding mode 0000000300000003 == 0000000300000003? yes
580 FPSCR decimal floating point rounding mode 0000000400000003 == 0000000400000003? yes
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td273 let Defs = [FPSCR] in {
302 } // Defs = [FPSCR]
322 let Defs = [FPSCR] in {
363 } // Defs = [FPSCR]
754 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
755 let Uses = [FPSCR] in {
1064 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1066 let Defs = [CPSR], Uses = [FPSCR], Rt = 0b1111 /* apsr_nzcv */ in
1070 // Application level FPSCR -> GPR
1071 let hasSideEffects = 1, Uses = [FPSCR] in
[all …]
DARMRegisterInfo.td187 def FPSCR : ARMReg<3, "fpscr">;
DARMFastISel.cpp1236 CondReg = ARM::FPSCR; in SelectCmp()
1240 CondReg = ARM::FPSCR; in SelectCmp()
DARMBaseRegisterInfo.cpp109 Reserved.set(ARM::FPSCR); in getReservedRegs()
DARMInstrThumb.td408 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
460 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
/external/llvm/lib/Target/PowerPC/
DREADME_P9.txt257 rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
262 rnd ← bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v)
267 rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
272 rnd ← bfp_NEGATE(bfp_ROUND_TO_BFP128(RO, FPSCR.RN, v))
DPPCInstrInfo.td112 // Extract FPSCR (not modeled at the DAG level).
2416 // to manipulate FPSCR. Note that FPSCR is not modeled at the DAG level.
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td159 // We model fpscr with two registers: FPSCR models the control bits and will be
167 def FPSCR : ARMReg<3, "fpscr">;
169 let Aliases = [FPSCR];
DARMInstrVFP.td1470 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
1471 let Uses = [FPSCR] in {
2070 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
2076 // Application level FPSCR -> GPR
2077 let hasSideEffects = 1, Uses = [FPSCR] in
2083 let Uses = [FPSCR] in {
2121 let Defs = [FPSCR] in {
2122 // Application level GPR -> FPSCR
DARMBaseRegisterInfo.cpp168 Reserved.set(ARM::FPSCR); in getReservedRegs()
DARMScheduleSwift.td640 // 4.2.38 Advanced SIMD and VFP, Move FPSCR
/external/vixl/src/aarch32/
Dinstructions-aarch32.cc365 case FPSCR: in GetName()
Dinstructions-aarch32.h896 FPSCR = 0x1, enumerator
911 case FPSCR: in SpecialFPRegister()
Dmacro-assembler-aarch32.cc799 Vmrs(RegisterOrAPSR_nzcv(tmp.GetCode()), FPSCR); in Printf()
895 Vmsr(FPSCR, tmp); in Printf()
/external/valgrind/VEX/priv/
Dhost_arm_defs.c1392 i->ARMin.FPSCR.toFPSCR = toFPSCR; in ARMInstr_FPSCR()
1393 i->ARMin.FPSCR.iReg = iReg; in ARMInstr_FPSCR()
1917 if (i->ARMin.FPSCR.toFPSCR) { in ppARMInstr()
1919 ppHRegARM(i->ARMin.FPSCR.iReg); in ppARMInstr()
1922 ppHRegARM(i->ARMin.FPSCR.iReg); in ppARMInstr()
2321 if (i->ARMin.FPSCR.toFPSCR) in getRegUsage_ARMInstr()
2322 addHRegUse(u, HRmRead, i->ARMin.FPSCR.iReg); in getRegUsage_ARMInstr()
2324 addHRegUse(u, HRmWrite, i->ARMin.FPSCR.iReg); in getRegUsage_ARMInstr()
2548 i->ARMin.FPSCR.iReg = lookupHRegRemap(m, i->ARMin.FPSCR.iReg); in mapRegs_ARMInstr()
3972 Bool toFPSCR = i->ARMin.FPSCR.toFPSCR; in emit_ARMInstr()
[all …]
Dhost_arm_defs.h878 } FPSCR; member
/external/libunwind/src/ptrace/
D_UPT_reg_offset.c423 [UNW_PPC32_FPSCR] = UNW_PPC_PT(FPSCR), \
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.td69 // bits in the FPSCR which is not modelled.
1120 // Instructions to manipulate FPSCR. Only long double handling uses these.
1121 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1134 // instruction had no outputs (because we aren't modelling the FPSCR) and
/external/vixl/test/aarch32/
Dtest-assembler-aarch32.cc2840 __ Vmsr(FPSCR, r0); in TEST()
2841 __ Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR); in TEST()
2844 __ Vmsr(FPSCR, r0); in TEST()
2845 __ Vmrs(RegisterOrAPSR_nzcv(r2.GetCode()), FPSCR); in TEST()
2848 __ Vmrs(RegisterOrAPSR_nzcv(pc.GetCode()), FPSCR); in TEST()
Dtest-disasm-a32.cc3490 COMPARE_BOTH(Vmsr(FPSCR, r0), "vmsr FPSCR, r0\n"); in TEST()
3492 COMPARE_BOTH(Vmrs(RegisterOrAPSR_nzcv(r1.GetCode()), FPSCR), in TEST()
3495 COMPARE_BOTH(Vmrs(RegisterOrAPSR_nzcv(pc.GetCode()), FPSCR), in TEST()
/external/valgrind/memcheck/
Dmc_machine.c873 if (o == GOF(FPSCR) && sz == 4) return -1; in get_otrack_shadow_offset_wrk()

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