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Searched refs:FRC (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCInstrQPX.td40 : AForm_1<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
41 !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), IIC_FPFused,
42 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
45 : AForm_1<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
46 !strconcat(opc, " $FRT, $FRA, $FRC, $FRB"), IIC_VecPerm,
47 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRB, v4f64:$FRC))]>;
55 : AForm_3<opcode, xo, (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC),
56 !strconcat(opc, " $FRT, $FRA, $FRC"), IIC_FPGeneral,
57 [(set v4f64:$FRT, (IntID v4f64:$FRA, v4f64:$FRC))]>;
156 (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC),
[all …]
DPPCInstrInfo.td2532 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2533 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2534 [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
2536 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
2537 "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2538 [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
2540 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
2541 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2543 (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
2545 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
[all …]
DPPCInstrFormats.td1520 bits<5> FRC;
1530 let Inst{21-25} = FRC;
1538 let FRC = 0;
1570 let FRC = 0;
/external/llvm/test/CodeGen/AMDGPU/
Dfract.f64.ll12 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
15 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
39 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
42 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
67 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
70 ; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
/external/clang/test/Profile/
Dobjc-general.m34 // PGOGEN: @[[FRC:"__profc_objc_general.m_\+\[A foreach_\]"]] = private global [2 x i64] zeroinitia…
45 // PGOGEN: store {{.*}} @[[FRC]], i64 0, i64 0
49 // PGOGEN: store {{.*}} @[[FRC]], i64 0, i64 1
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.td1226 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1227 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
1228 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
1232 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1233 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
1234 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1238 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
1239 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
1240 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
1244 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
[all …]
DPPCInstrFormats.td669 bits<5> FRC;
679 let Inst{21-25} = FRC;
687 let FRC = 0;
/external/mesa3d/src/gallium/tests/graw/fragment-shader/
Dfrag-frc.sh11 FRC OUT[0], TEMP[0]
/external/mesa3d/src/gallium/tests/graw/vertex-shader/
Dvert-frc.sh13 FRC OUT[1], TEMP[0]
/external/llvm/lib/Target/X86/
DX86InstrAVX512.td123 RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);
803 (ins SrcInfo.FRC:$src), OpcodeStr#"\t{$src, $dst|$dst, $src}",
804 [(set DestInfo.RC:$dst, (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)))]>,
809 (ins DestInfo.RC:$src0, DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
813 (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
818 (ins DestInfo.KRCWM:$mask, SrcInfo.FRC:$src),
822 (DestInfo.VT (X86VBroadcast SrcInfo.FRC:$src)),
1406 (outs _.KRC:$dst), (ins _.FRC:$src1, _.FRC:$src2, AVXCC:$cc),
1409 [(set _.KRC:$dst, (OpNode _.FRC:$src1,
1410 _.FRC:$src2,
[all …]
/external/mesa3d/src/mesa/program/
Dprogram_lexer.l199 FRC{sat} { return_opcode( 1, VECTOR_OP, FRC, 3); }
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_opcode_tmp.h79 OP11(FRC)
Dtgsi_lowering.c1642 OPCS(FRC) || in tgsi_transform_lowering()
1683 if (OPCS(FRC)) { in tgsi_transform_lowering()
1684 newlen += FRC_GROW * OPCS(FRC); in tgsi_transform_lowering()
/external/llvm/lib/Target/Hexagon/
DHexagonBitSimplify.cpp1293 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); in processBlock() local
1294 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock()
1554 auto *FRC = HBS::getFinalVRegClass(MR, MRI); in processBlock() local
1555 unsigned NewR = MRI.createVirtualRegister(FRC); in processBlock()
2152 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI); in processBlock() local
2155 if (FRC->getID() == Hexagon::DoubleRegsRegClassID) { in processBlock()
2161 if (FRC->getID() == Hexagon::IntRegsRegClassID) { in processBlock()
2169 if (FRC->getID() == Hexagon::PredRegsRegClassID) { in processBlock()
/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_disasm.c482 OPC(FRC),
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_vec4.h195 EMIT1(FRC)
Dbrw_vec4_builder.h418 ALU1(FRC) in ALU2_ACC()
Dbrw_fs_builder.h472 ALU1(FRC) in ALU2_ACC()
Dbrw_eu.h167 ALU1(FRC)
Dbrw_vec4_visitor.cpp159 ALU1(FRC) in ALU1()
Dbrw_vec4_nir.cpp1522 inst = emit(FRC(dst, op[0])); in nir_emit_alu()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_vertprog.c81 OPN(FRC, 1),
/external/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnvfx_vertprog.c606 nvfx_vp_emit(vpc, arith(sat, VEC, FRC, dst, mask, src[0], none, none)); in nvfx_vertprog_parse_instruction()
Dnvfx_fragprog.c608 nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none)); in nvfx_fragprog_parse_instruction()
/external/mesa3d/src/gallium/state_trackers/nine/
Dnine_shader.c2913 _OPI(FRC, FRC, V(0,0), V(3,0), V(0,0), V(3,0), 1, 1, NULL), /* 19 */

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