/external/llvm/test/CodeGen/X86/ |
D | frem-msvc32.ll | 1 ; Make sure that 32-bit FREM is promoted to 64-bit FREM on 32-bit MSVC.
|
/external/javassist/src/main/javassist/bytecode/ |
D | Opcode.java | 103 int FREM = 114; field
|
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 235 FADD, FSUB, FMUL, FMA, FDIV, FREM, enumerator
|
/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 241 FADD, FSUB, FMUL, FDIV, FREM, enumerator
|
/external/llvm/lib/Target/AMDGPU/ |
D | AMDGPUTargetTransformInfo.cpp | 175 case ISD::FREM: in getArithmeticInstrCost()
|
D | AMDGPUISelLowering.cpp | 255 setOperationAction(ISD::FREM, MVT::f32, Custom); in AMDGPUTargetLowering() 256 setOperationAction(ISD::FREM, MVT::f64, Custom); in AMDGPUTargetLowering() 416 setOperationAction(ISD::FREM, VT, Expand); in AMDGPUTargetLowering() 712 case ISD::FREM: return LowerFREM(Op, DAG); in LowerOperation()
|
/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/ |
D | LabelFlowAnalyzerTest.java | 206 testInsn(FREM, true); in testInsn()
|
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 150 case ISD::FREM: in LegalizeOp()
|
D | SelectionDAGBuilder.h | 486 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
|
D | LegalizeVectorTypes.cpp | 103 case ISD::FREM: in ScalarizeVectorResult() 492 case ISD::FREM: in SplitVectorResult() 1257 case ISD::FREM: in WidenVectorResult()
|
D | FastISel.cpp | 908 return SelectBinaryOp(I, ISD::FREM); in SelectOperator()
|
D | SelectionDAG.cpp | 2738 case ISD::FREM: in getNode() 2997 case ISD::FREM : in getNode() 3021 case ISD::FREM: in getNode() 3061 case ISD::FREM: in getNode() 5998 case ISD::FREM: return "frem"; in getOperationName()
|
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
D | SystemZISelLowering.cpp | 144 setOperationAction(ISD::FREM, MVT::f32, Expand); in SystemZTargetLowering() 145 setOperationAction(ISD::FREM, MVT::f64, Expand); in SystemZTargetLowering()
|
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaISelLowering.cpp | 80 setOperationAction(ISD::FREM, MVT::f32, Expand); in AlphaTargetLowering() 81 setOperationAction(ISD::FREM, MVT::f64, Expand); in AlphaTargetLowering()
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 202 case ISD::FREM: return "frem"; in getOperationName()
|
D | SelectionDAGBuilder.h | 837 void visitFRem(const User &I) { visitBinary(I, ISD::FREM); } in visitFRem()
|
D | LegalizeFloatTypes.cpp | 99 case ISD::FREM: R = SoftenFloatRes_FREM(N); break; in SoftenFloatResult() 1046 case ISD::FREM: ExpandFloatRes_FREM(N, Lo, Hi); break; in ExpandFloatResult() 1895 case ISD::FREM: in PromoteFloatResult()
|
D | LegalizeVectorOps.cpp | 275 case ISD::FREM: in LegalizeOp()
|
/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyISelLowering.cpp | 82 ISD::FREM, ISD::FMA}) in WebAssemblyTargetLowering()
|
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 758 setOperationAction(ISD::FREM , MVT::f64, Expand); in SparcTargetLowering() 762 setOperationAction(ISD::FREM , MVT::f32, Expand); in SparcTargetLowering()
|
/external/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 967 case ISD::FREM: in canOpTrap() 1683 case FRem: return ISD::FREM; in InstructionOpcodeToISD()
|
/external/r8/src/main/java/com/android/tools/r8/ir/conversion/ |
D | JarSourceCode.java | 1047 case Opcodes.FREM: in opType() 1313 case Opcodes.FREM: in updateState() 2040 case Opcodes.FREM: in build()
|
/external/javassist/src/main/javassist/bytecode/analysis/ |
D | Executor.java | 360 case FREM: in execute()
|
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
D | MBlazeISelLowering.cpp | 72 setOperationAction(ISD::FREM, MVT::f32, Expand); in MBlazeTargetLowering()
|
/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 132 setOperationAction(ISD::FREM, MVT::f32, Expand); in AArch64TargetLowering() 133 setOperationAction(ISD::FREM, MVT::f64, Expand); in AArch64TargetLowering() 134 setOperationAction(ISD::FREM, MVT::f80, Expand); in AArch64TargetLowering() 152 setOperationAction(ISD::FREM, MVT::f128, Expand); in AArch64TargetLowering() 270 setOperationAction(ISD::FREM, MVT::f16, Promote); in AArch64TargetLowering() 325 setOperationAction(ISD::FREM, MVT::v4f16, Expand); in AArch64TargetLowering() 357 setOperationAction(ISD::FREM, MVT::v8f16, Expand); in AArch64TargetLowering() 535 setOperationAction(ISD::FREM, MVT::v1f64, Expand); in AArch64TargetLowering() 692 setOperationAction(ISD::FREM, VT, Expand); in addTypeForNEON()
|