| /external/strace/xlat/ |
| D | open_mode_flags.h | 97 #if defined(FTRUNC) || (defined(HAVE_DECL_FTRUNC) && HAVE_DECL_FTRUNC)
98 XLAT(FTRUNC),
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| D | open_mode_flags.in | 34 FTRUNC
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| /external/python/cpython2/Lib/plat-irix5/ |
| D | FILE.py | 155 FTRUNC = 0x0200 variable
219 FTRUNC = 0x0200 variable
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| /external/python/cpython2/Lib/plat-irix6/ |
| D | FILE.py | 562 FTRUNC = 0x0200 variable
657 FTRUNC = 0x0200 variable
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 452 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| D | BasicTTIImpl.h | 788 ISDs.push_back(ISD::FTRUNC); in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 304 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break; in mightUseCTR()
368 Opcode = ISD::FTRUNC; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 151 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); in PPCTargetLowering()
210 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
215 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
475 setOperationAction(ISD::FTRUNC, VT, Expand); in PPCTargetLowering()
521 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
580 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
800 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal); in PPCTargetLowering()
805 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 245 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in AMDGPUTargetLowering()
278 setOperationAction(ISD::FTRUNC, MVT::f64, Custom); in AMDGPUTargetLowering()
419 setOperationAction(ISD::FTRUNC, VT, Expand); in AMDGPUTargetLowering()
714 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG); in LowerOperation()
1287 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq); in LowerDIVREM24()
1597 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div); in LowerFREM()
1611 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFCEIL()
1731 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X); in LowerFROUND32()
1832 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFFLOOR()
2047 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src); in LowerFP64_TO_INT()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 185 case ISD::FTRUNC: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 88 case ISD::FTRUNC: in ScalarizeVectorResult()
465 case ISD::FTRUNC: in SplitVectorResult()
989 case ISD::FTRUNC: in SplitVectorOperand()
1312 case ISD::FTRUNC: in WidenVectorResult()
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| D | LegalizeFloatTypes.cpp | 92 case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break; in SoftenFloatResult()
872 case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break; in ExpandFloatResult()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 162 case ISD::FTRUNC: return "ftrunc"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 105 case ISD::FTRUNC: R = SoftenFloatRes_FTRUNC(N); break; in SoftenFloatResult()
1042 case ISD::FTRUNC: ExpandFloatRes_FTRUNC(N, Lo, Hi); break; in ExpandFloatResult()
1884 case ISD::FTRUNC: R = PromoteFloatRes_UnaryOp(N); break; in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 319 case ISD::FTRUNC: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 95 case ISD::FTRUNC: in ScalarizeVectorResult()
654 case ISD::FTRUNC: in SplitVectorResult()
1505 case ISD::FTRUNC: in SplitVectorOperand()
2168 case ISD::FTRUNC: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3856 case ISD::FTRUNC: in ConvertNodeToLibcall()
4226 case ISD::FTRUNC: in PromoteNode()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 158 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); in AArch64TargetLowering()
291 setOperationAction(ISD::FTRUNC, MVT::f16, Promote); in AArch64TargetLowering()
331 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand); in AArch64TargetLowering()
364 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand); in AArch64TargetLowering()
382 setOperationAction(ISD::FTRUNC, Ty, Legal); in AArch64TargetLowering()
542 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand); in AArch64TargetLowering()
626 setOperationAction(ISD::FTRUNC, Ty, Legal); in AArch64TargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 933 setOperationAction(ISD::FTRUNC, VT, Expand); in initActions()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 379 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 449 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 511 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); in ARMTargetLowering()
528 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand); in ARMTargetLowering()
545 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand); in ARMTargetLowering()
674 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); in ARMTargetLowering()
991 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in ARMTargetLowering()
1005 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in ARMTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 365 setOperationAction(ISD::FTRUNC, VT, Legal); in SystemZTargetLowering()
404 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in SystemZTargetLowering()
|