| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 223 unsigned FirstReg = 0; in CreateRegs() local
231 if (!FirstReg) FirstReg = R; in CreateRegs()
234 return FirstReg; in CreateRegs()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 382 unsigned FirstReg = 0; in CreateRegs() local
390 if (!FirstReg) FirstReg = R; in CreateRegs()
393 return FirstReg; in CreateRegs()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 494 unsigned FirstReg = 0; in ScanInstruction() local
501 if (FirstReg != 0) { in ScanInstruction()
503 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
506 FirstReg = Reg; in ScanInstruction()
510 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 487 unsigned FirstReg = 0; in ScanInstruction() local
494 if (FirstReg != 0) { in ScanInstruction()
496 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
499 FirstReg = Reg; in ScanInstruction()
503 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n'); in ScanInstruction()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2057 unsigned &FirstReg, in CanFormLdStDWord() argument
2119 FirstReg = Op0->getOperand(0).getReg(); in CanFormLdStDWord()
2121 if (FirstReg == SecondReg) in CanFormLdStDWord()
2217 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
2225 FirstReg, SecondReg, BaseReg, in RescheduleOps()
2232 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2238 .addReg(FirstReg, RegState::Define) in RescheduleOps()
2252 .addReg(FirstReg) in RescheduleOps()
2270 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2271 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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| D | ARMBaseInstrInfo.cpp | 2072 unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); in tryFoldSPUpdateIntoPushPop() local
2093 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded; in tryFoldSPUpdateIntoPushPop()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
797 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
798 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
800 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
802 unsigned OldFirstReg = FirstReg; in insertSelect()
803 FirstReg = MRI.createVirtualRegister(FirstRC); in insertSelect()
804 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg) in insertSelect()
809 .addReg(FirstReg).addReg(SecondReg) in insertSelect()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1202 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands() local
1205 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0)); in addVectorList64Operands()
1215 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands() local
1218 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0)); in addVectorList128Operands()
2979 int64_t FirstReg = tryMatchVectorRegister(Kind, true); in parseVectorList() local
2980 if (FirstReg == -1) in parseVectorList()
2982 int64_t PrevReg = FirstReg; in parseVectorList()
3041 FirstReg, Count, NumElements, ElementKind, S, getLoc(), getContext())); in parseVectorList()
4616 int FirstReg = tryParseRegister(); in tryParseGPRSeqPair() local
4617 if (FirstReg == -1) { in tryParseGPRSeqPair()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3724 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs() argument
3729 unsigned NumRegs = LastReg - FirstReg; in copyByValRegs()
3738 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); in copyByValRegs()
3756 unsigned ArgReg = ByValArgRegs[FirstReg + I]; in copyByValRegs()
3773 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg() argument
3782 unsigned NumRegs = LastReg - FirstReg; in passByValArg()
3797 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3847 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
3922 unsigned FirstReg = 0; in HandleByVal() local
3938 FirstReg = State->getFirstUnallocated(IntArgRegs); in HandleByVal()
[all …]
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| D | MipsISelLowering.h | 468 const Argument *FuncArg, unsigned FirstReg,
477 unsigned FirstReg, unsigned LastReg,
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1307 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1308 Reg = FirstReg; in printVectorList()
1309 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1310 Reg = FirstReg; in printVectorList()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 1935 const auto FirstReg = in legalizeMov() local
1939 SrcGPRHi = Target->makeReg(IceType_i32, FirstReg); in legalizeMov()
2007 const auto FirstReg = in legalizeMov() local
2011 Variable *SrcGPRHi = Target->makeReg(IceType_i32, FirstReg); in legalizeMov()
2094 const auto FirstReg = in legalizeMov() local
2098 Variable *DstGPRHi = Target->makeReg(IceType_i32, FirstReg); in legalizeMov()
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| D | IceTargetLoweringARM32.cpp | 406 const auto FirstReg = in copyRegAllocFromInfWeightVariable64On32() local
415 Lo->setRegNum(FirstReg); in copyRegAllocFromInfWeightVariable64On32()
417 Hi->setRegNum(RegNumT::fixme(FirstReg + 1)); in copyRegAllocFromInfWeightVariable64On32()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3707 unsigned FirstReg = Reg; in parseVectorList() local
3711 FirstReg = Reg = getDRegFromQReg(Reg); in parseVectorList()
3853 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
3856 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, in parseVectorList()
3866 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); in parseVectorList()
3868 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, in parseVectorList()
3873 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, in parseVectorList()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3139 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
3156 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
3164 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
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