| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
136 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
139 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
142 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
145 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
148 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
[all …]
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| D | PPCInstrAltivec.td | 209 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
212 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
215 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
218 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
591 def : Pat<(int_ppc_altivec_dst G8RC:$rA, GPRC:$rB, imm:$STRM),
592 (DST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
593 def : Pat<(int_ppc_altivec_dstt G8RC:$rA, GPRC:$rB, imm:$STRM),
594 (DSTT64 1, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
595 def : Pat<(int_ppc_altivec_dstst G8RC:$rA, GPRC:$rB, imm:$STRM),
596 (DSTST64 0, imm:$STRM, (i64 G8RC:$rA), GPRC:$rB)>;
[all …]
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| D | PPCRegisterInfo.cpp | 370 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerDynamicAlloc() local
372 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; in lowerDynamicAlloc()
463 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRSpilling() local
465 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; in lowerCRSpilling()
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| D | PPCFrameLowering.cpp | 775 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in processFunctionBeforeCalleeSavedScan() local
776 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; in processFunctionBeforeCalleeSavedScan()
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| D | PPCRegisterInfo.td | 283 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
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| D | PPCInstrInfo.td | 386 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 381 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerDynamicAlloc() local
383 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
407 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
415 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
501 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRSpilling() local
504 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
516 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
546 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in lowerCRRestore() local
549 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
561 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
[all …]
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| D | PPCRegisterInfo.td | 245 def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
250 let AltOrders = [(add (sub G8RC, X2), X2)];
270 def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
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| D | PPCFrameLowering.cpp | 1692 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; in addScavengingSpillSlot() local
1693 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
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| D | PPCInstrQPX.td | 626 (outs qfrc:$FRT), (ins G8RC:$src),
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| D | PPCInstrInfo.td | 414 def g8rc : RegisterOperand<G8RC> {
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