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1 #ifndef GEN_RENDER_3D_XML
2 #define GEN_RENDER_3D_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 https://github.com/olvaffe/envytools/
8 git clone https://github.com/olvaffe/envytools.git
9 
10 Copyright (C) 2014-2015 by the following authors:
11 - Chia-I Wu <olvaffe@gmail.com> (olv)
12 
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20 
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
24 
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 */
33 
34 
35 enum gen_3dprim_type {
36     GEN6_3DPRIM_POINTLIST				      = 0x1,
37     GEN6_3DPRIM_LINELIST				      = 0x2,
38     GEN6_3DPRIM_LINESTRIP				      = 0x3,
39     GEN6_3DPRIM_TRILIST					      = 0x4,
40     GEN6_3DPRIM_TRISTRIP				      = 0x5,
41     GEN6_3DPRIM_TRIFAN					      = 0x6,
42     GEN6_3DPRIM_QUADLIST				      = 0x7,
43     GEN6_3DPRIM_QUADSTRIP				      = 0x8,
44     GEN6_3DPRIM_LINELIST_ADJ				      = 0x9,
45     GEN6_3DPRIM_LINESTRIP_ADJ				      = 0xa,
46     GEN6_3DPRIM_TRILIST_ADJ				      = 0xb,
47     GEN6_3DPRIM_TRISTRIP_ADJ				      = 0xc,
48     GEN6_3DPRIM_TRISTRIP_REVERSE			      = 0xd,
49     GEN6_3DPRIM_POLYGON					      = 0xe,
50     GEN6_3DPRIM_RECTLIST				      = 0xf,
51     GEN6_3DPRIM_LINELOOP				      = 0x10,
52     GEN6_3DPRIM_POINTLIST_BF				      = 0x11,
53     GEN6_3DPRIM_LINESTRIP_CONT				      = 0x12,
54     GEN6_3DPRIM_LINESTRIP_BF				      = 0x13,
55     GEN6_3DPRIM_LINESTRIP_CONT_BF			      = 0x14,
56     GEN6_3DPRIM_TRIFAN_NOSTIPPLE			      = 0x16,
57     GEN7_3DPRIM_PATCHLIST_1				      = 0x20,
58     GEN7_3DPRIM_PATCHLIST_2				      = 0x21,
59     GEN7_3DPRIM_PATCHLIST_3				      = 0x22,
60     GEN7_3DPRIM_PATCHLIST_4				      = 0x23,
61     GEN7_3DPRIM_PATCHLIST_5				      = 0x24,
62     GEN7_3DPRIM_PATCHLIST_6				      = 0x25,
63     GEN7_3DPRIM_PATCHLIST_7				      = 0x26,
64     GEN7_3DPRIM_PATCHLIST_8				      = 0x27,
65     GEN7_3DPRIM_PATCHLIST_9				      = 0x28,
66     GEN7_3DPRIM_PATCHLIST_10				      = 0x29,
67     GEN7_3DPRIM_PATCHLIST_11				      = 0x2a,
68     GEN7_3DPRIM_PATCHLIST_12				      = 0x2b,
69     GEN7_3DPRIM_PATCHLIST_13				      = 0x2c,
70     GEN7_3DPRIM_PATCHLIST_14				      = 0x2d,
71     GEN7_3DPRIM_PATCHLIST_15				      = 0x2e,
72     GEN7_3DPRIM_PATCHLIST_16				      = 0x2f,
73     GEN7_3DPRIM_PATCHLIST_17				      = 0x30,
74     GEN7_3DPRIM_PATCHLIST_18				      = 0x31,
75     GEN7_3DPRIM_PATCHLIST_19				      = 0x32,
76     GEN7_3DPRIM_PATCHLIST_20				      = 0x33,
77     GEN7_3DPRIM_PATCHLIST_21				      = 0x34,
78     GEN7_3DPRIM_PATCHLIST_22				      = 0x35,
79     GEN7_3DPRIM_PATCHLIST_23				      = 0x36,
80     GEN7_3DPRIM_PATCHLIST_24				      = 0x37,
81     GEN7_3DPRIM_PATCHLIST_25				      = 0x38,
82     GEN7_3DPRIM_PATCHLIST_26				      = 0x39,
83     GEN7_3DPRIM_PATCHLIST_27				      = 0x3a,
84     GEN7_3DPRIM_PATCHLIST_28				      = 0x3b,
85     GEN7_3DPRIM_PATCHLIST_29				      = 0x3c,
86     GEN7_3DPRIM_PATCHLIST_30				      = 0x3d,
87     GEN7_3DPRIM_PATCHLIST_31				      = 0x3e,
88     GEN7_3DPRIM_PATCHLIST_32				      = 0x3f,
89 };
90 
91 enum gen_state_alignment {
92     GEN6_ALIGNMENT_COLOR_CALC_STATE			      = 0x40,
93     GEN6_ALIGNMENT_DEPTH_STENCIL_STATE			      = 0x40,
94     GEN6_ALIGNMENT_BLEND_STATE				      = 0x40,
95     GEN6_ALIGNMENT_CLIP_VIEWPORT			      = 0x20,
96     GEN6_ALIGNMENT_SF_VIEWPORT				      = 0x20,
97     GEN7_ALIGNMENT_SF_CLIP_VIEWPORT			      = 0x40,
98     GEN6_ALIGNMENT_CC_VIEWPORT				      = 0x20,
99     GEN6_ALIGNMENT_SCISSOR_RECT				      = 0x20,
100     GEN6_ALIGNMENT_BINDING_TABLE_STATE			      = 0x20,
101     GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR_STATE		      = 0x20,
102     GEN8_ALIGNMENT_SAMPLER_BORDER_COLOR_STATE		      = 0x40,
103     GEN6_ALIGNMENT_SAMPLER_STATE			      = 0x20,
104     GEN6_ALIGNMENT_SURFACE_STATE			      = 0x20,
105     GEN8_ALIGNMENT_SURFACE_STATE			      = 0x40,
106 };
107 
108 enum gen_index_format {
109     GEN6_INDEX_BYTE					      = 0x0,
110     GEN6_INDEX_WORD					      = 0x1,
111     GEN6_INDEX_DWORD					      = 0x2,
112 };
113 
114 enum gen_vf_component {
115     GEN6_VFCOMP_NOSTORE					      = 0x0,
116     GEN6_VFCOMP_STORE_SRC				      = 0x1,
117     GEN6_VFCOMP_STORE_0					      = 0x2,
118     GEN6_VFCOMP_STORE_1_FP				      = 0x3,
119     GEN6_VFCOMP_STORE_1_INT				      = 0x4,
120     GEN6_VFCOMP_STORE_VID				      = 0x5,
121     GEN6_VFCOMP_STORE_IID				      = 0x6,
122 };
123 
124 enum gen_depth_format {
125     GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT			      = 0x0,
126     GEN6_ZFORMAT_D32_FLOAT				      = 0x1,
127     GEN6_ZFORMAT_D24_UNORM_S8_UINT			      = 0x2,
128     GEN6_ZFORMAT_D24_UNORM_X8_UINT			      = 0x3,
129     GEN6_ZFORMAT_D16_UNORM				      = 0x5,
130 };
131 
132 enum gen_reorder_mode {
133     GEN7_REORDER_LEADING				      = 0x0,
134     GEN7_REORDER_TRAILING				      = 0x1,
135 };
136 
137 enum gen_clip_mode {
138     GEN6_CLIPMODE_NORMAL				      = 0x0,
139     GEN6_CLIPMODE_REJECT_ALL				      = 0x3,
140     GEN6_CLIPMODE_ACCEPT_ALL				      = 0x4,
141 };
142 
143 enum gen_front_winding {
144     GEN6_FRONTWINDING_CW				      = 0x0,
145     GEN6_FRONTWINDING_CCW				      = 0x1,
146 };
147 
148 enum gen_fill_mode {
149     GEN6_FILLMODE_SOLID					      = 0x0,
150     GEN6_FILLMODE_WIREFRAME				      = 0x1,
151     GEN6_FILLMODE_POINT					      = 0x2,
152 };
153 
154 enum gen_cull_mode {
155     GEN6_CULLMODE_BOTH					      = 0x0,
156     GEN6_CULLMODE_NONE					      = 0x1,
157     GEN6_CULLMODE_FRONT					      = 0x2,
158     GEN6_CULLMODE_BACK					      = 0x3,
159 };
160 
161 enum gen_pixel_location {
162     GEN6_PIXLOC_CENTER					      = 0x0,
163     GEN6_PIXLOC_UL_CORNER				      = 0x1,
164 };
165 
166 enum gen_sample_count {
167     GEN6_NUMSAMPLES_1					      = 0x0,
168     GEN8_NUMSAMPLES_2					      = 0x1,
169     GEN6_NUMSAMPLES_4					      = 0x2,
170     GEN7_NUMSAMPLES_8					      = 0x3,
171 };
172 
173 enum gen_inputattr_select {
174     GEN6_INPUTATTR_NORMAL				      = 0x0,
175     GEN6_INPUTATTR_FACING				      = 0x1,
176     GEN6_INPUTATTR_W					      = 0x2,
177     GEN6_INPUTATTR_FACING_W				      = 0x3,
178 };
179 
180 enum gen_zw_interp {
181     GEN6_ZW_INTERP_PIXEL				      = 0x0,
182     GEN6_ZW_INTERP_CENTROID				      = 0x2,
183     GEN6_ZW_INTERP_SAMPLE				      = 0x3,
184 };
185 
186 enum gen_position_offset {
187     GEN6_POSOFFSET_NONE					      = 0x0,
188     GEN6_POSOFFSET_CENTROID				      = 0x2,
189     GEN6_POSOFFSET_SAMPLE				      = 0x3,
190 };
191 
192 enum gen_edsc_mode {
193     GEN7_EDSC_NORMAL					      = 0x0,
194     GEN7_EDSC_PSEXEC					      = 0x1,
195     GEN7_EDSC_PREPS					      = 0x2,
196 };
197 
198 enum gen_pscdepth_mode {
199     GEN7_PSCDEPTH_OFF					      = 0x0,
200     GEN7_PSCDEPTH_ON					      = 0x1,
201     GEN7_PSCDEPTH_ON_GE					      = 0x2,
202     GEN7_PSCDEPTH_ON_LE					      = 0x3,
203 };
204 
205 enum gen_msrast_mode {
206     GEN6_MSRASTMODE_OFF_PIXEL				      = 0x0,
207     GEN6_MSRASTMODE_OFF_PATTERN				      = 0x1,
208     GEN6_MSRASTMODE_ON_PIXEL				      = 0x2,
209     GEN6_MSRASTMODE_ON_PATTERN				      = 0x3,
210 };
211 
212 #define GEN6_INTERP_NONPERSPECTIVE_SAMPLE			(0x1 << 5)
213 #define GEN6_INTERP_NONPERSPECTIVE_CENTROID			(0x1 << 4)
214 #define GEN6_INTERP_NONPERSPECTIVE_PIXEL			(0x1 << 3)
215 #define GEN6_INTERP_PERSPECTIVE_SAMPLE				(0x1 << 2)
216 #define GEN6_INTERP_PERSPECTIVE_CENTROID			(0x1 << 1)
217 #define GEN6_INTERP_PERSPECTIVE_PIXEL				(0x1 << 0)
218 #define GEN6_PS_DISPATCH_32					(0x1 << 2)
219 #define GEN6_PS_DISPATCH_16					(0x1 << 1)
220 #define GEN6_PS_DISPATCH_8					(0x1 << 0)
221 #define GEN6_THREADDISP_SPF					(0x1 << 31)
222 #define GEN6_THREADDISP_VME					(0x1 << 30)
223 #define GEN6_THREADDISP_SAMPLER_COUNT__MASK			0x38000000
224 #define GEN6_THREADDISP_SAMPLER_COUNT__SHIFT			27
225 #define GEN7_THREADDISP_DENORMAL__MASK				0x04000000
226 #define GEN7_THREADDISP_DENORMAL__SHIFT				26
227 #define GEN7_THREADDISP_DENORMAL_FTZ				(0x0 << 26)
228 #define GEN7_THREADDISP_DENORMAL_RET				(0x1 << 26)
229 #define GEN6_THREADDISP_BINDING_TABLE_SIZE__MASK		0x03fc0000
230 #define GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT		18
231 #define GEN6_THREADDISP_PRIORITY_HIGH				(0x1 << 17)
232 #define GEN6_THREADDISP_FP_MODE_ALT				(0x1 << 16)
233 #define GEN7_ROUNDING_MODE__MASK				0x0000c000
234 #define GEN7_ROUNDING_MODE__SHIFT				14
235 #define GEN7_ROUNDING_MODE_RTNE					(0x0 << 14)
236 #define GEN7_ROUNDING_MODE_RU					(0x1 << 14)
237 #define GEN7_ROUNDING_MODE_RD					(0x2 << 14)
238 #define GEN7_ROUNDING_MODE_RTZ					(0x3 << 14)
239 #define GEN6_THREADDISP_ILLEGAL_CODE_EXCEPTION			(0x1 << 13)
240 #define GEN75_THREADDISP_ACCESS_UAV				(0x1 << 12)
241 #define GEN6_THREADDISP_MASK_STACK_EXCEPTION			(0x1 << 11)
242 #define GEN6_THREADDISP_SOFTWARE_EXCEPTION			(0x1 << 7)
243 #define GEN6_THREADSCRATCH_ADDR__MASK				0xfffffc00
244 #define GEN6_THREADSCRATCH_ADDR__SHIFT				10
245 #define GEN6_THREADSCRATCH_ADDR__SHR				10
246 #define GEN6_THREADSCRATCH_SPACE_PER_THREAD__MASK		0x0000000f
247 #define GEN6_THREADSCRATCH_SPACE_PER_THREAD__SHIFT		0
248 #define GEN6_3DSTATE_VF_STATISTICS__SIZE			1
249 
250 #define GEN6_VF_STATS_DW0_ENABLE				(0x1 << 0)
251 
252 #define GEN6_3DSTATE_BINDING_TABLE_POINTERS__SIZE		4
253 
254 #define GEN6_BINDING_TABLE_PTR_DW0_PS_CHANGED			(0x1 << 12)
255 #define GEN6_BINDING_TABLE_PTR_DW0_GS_CHANGED			(0x1 << 9)
256 #define GEN6_BINDING_TABLE_PTR_DW0_VS_CHANGED			(0x1 << 8)
257 
258 
259 
260 
261 #define GEN6_3DSTATE_SAMPLER_STATE_POINTERS__SIZE		4
262 
263 #define GEN6_SAMPLER_PTR_DW0_PS_CHANGED				(0x1 << 12)
264 #define GEN6_SAMPLER_PTR_DW0_GS_CHANGED				(0x1 << 9)
265 #define GEN6_SAMPLER_PTR_DW0_VS_CHANGED				(0x1 << 8)
266 
267 #define GEN6_SAMPLER_PTR_DW1_VS_ADDR__MASK			0xffffffe0
268 #define GEN6_SAMPLER_PTR_DW1_VS_ADDR__SHIFT			5
269 #define GEN6_SAMPLER_PTR_DW1_VS_ADDR__SHR			5
270 
271 #define GEN6_SAMPLER_PTR_DW2_GS_ADDR__MASK			0xffffffe0
272 #define GEN6_SAMPLER_PTR_DW2_GS_ADDR__SHIFT			5
273 #define GEN6_SAMPLER_PTR_DW2_GS_ADDR__SHR			5
274 
275 #define GEN6_SAMPLER_PTR_DW3_PS_ADDR__MASK			0xffffffe0
276 #define GEN6_SAMPLER_PTR_DW3_PS_ADDR__SHIFT			5
277 #define GEN6_SAMPLER_PTR_DW3_PS_ADDR__SHR			5
278 
279 #define GEN6_3DSTATE_URB__SIZE					3
280 
281 
282 #define GEN6_URB_DW1_VS_ENTRY_SIZE__MASK			0x00ff0000
283 #define GEN6_URB_DW1_VS_ENTRY_SIZE__SHIFT			16
284 #define GEN6_URB_DW1_VS_ENTRY_COUNT__MASK			0x0000ffff
285 #define GEN6_URB_DW1_VS_ENTRY_COUNT__SHIFT			0
286 #define GEN6_URB_DW1_VS_ENTRY_COUNT__ALIGN			4
287 
288 #define GEN6_URB_DW2_GS_ENTRY_COUNT__MASK			0x0003ff00
289 #define GEN6_URB_DW2_GS_ENTRY_COUNT__SHIFT			8
290 #define GEN6_URB_DW2_GS_ENTRY_COUNT__ALIGN			4
291 #define GEN6_URB_DW2_GS_ENTRY_SIZE__MASK			0x00000007
292 #define GEN6_URB_DW2_GS_ENTRY_SIZE__SHIFT			0
293 
294 #define GEN7_3DSTATE_URB_ANY__SIZE				2
295 
296 
297 #define GEN7_URB_DW1_OFFSET__MASK				0x3e000000
298 #define GEN7_URB_DW1_OFFSET__SHIFT				25
299 #define GEN75_URB_DW1_OFFSET__MASK				0x7e000000
300 #define GEN75_URB_DW1_OFFSET__SHIFT				25
301 #define GEN8_URB_DW1_OFFSET__MASK				0xfe000000
302 #define GEN8_URB_DW1_OFFSET__SHIFT				25
303 #define GEN7_URB_DW1_ENTRY_SIZE__MASK				0x01ff0000
304 #define GEN7_URB_DW1_ENTRY_SIZE__SHIFT				16
305 #define GEN7_URB_DW1_ENTRY_COUNT__MASK				0x0000ffff
306 #define GEN7_URB_DW1_ENTRY_COUNT__SHIFT				0
307 
308 #define GEN75_3DSTATE_GATHER_CONSTANT_ANY__SIZE			130
309 
310 
311 #define GEN75_GATHER_CONST_DW1_BT_VALID__MASK			0xffff0000
312 #define GEN75_GATHER_CONST_DW1_BT_VALID__SHIFT			16
313 #define GEN75_GATHER_CONST_DW1_BT_BLOCK__MASK			0x0000f000
314 #define GEN75_GATHER_CONST_DW1_BT_BLOCK__SHIFT			12
315 
316 #define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__MASK	0x007fffc0
317 #define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__SHIFT	6
318 #define GEN75_GATHER_CONST_DW2_GATHER_BUFFER_OFFSET__SHR	6
319 #define GEN8_GATHER_CONST_DW2_DX9_STALL				(0x1 << 5)
320 #define GEN75_GATHER_CONST_DW2_DX9_ENABLE			(0x1 << 4)
321 
322 #define GEN75_GATHER_CONST_DW_ENTRY_HIGH__MASK			0xffff0000
323 #define GEN75_GATHER_CONST_DW_ENTRY_HIGH__SHIFT			16
324 #define GEN75_GATHER_CONST_DW_ENTRY_OFFSET__MASK		0x0000ff00
325 #define GEN75_GATHER_CONST_DW_ENTRY_OFFSET__SHIFT		8
326 #define GEN75_GATHER_CONST_DW_ENTRY_CHANNEL_MASK__MASK		0x000000f0
327 #define GEN75_GATHER_CONST_DW_ENTRY_CHANNEL_MASK__SHIFT		4
328 #define GEN75_GATHER_CONST_DW_ENTRY_BT_INDEX__MASK		0x0000001f
329 #define GEN75_GATHER_CONST_DW_ENTRY_BT_INDEX__SHIFT		0
330 
331 #define GEN75_3DSTATE_BINDING_TABLE_EDIT_ANY__SIZE		258
332 
333 
334 #define GEN75_BT_EDIT_DW1_BT_BLOCK_CLEAR__MASK			0xffff0000
335 #define GEN75_BT_EDIT_DW1_BT_BLOCK_CLEAR__SHIFT			16
336 #define GEN75_BT_EDIT_DW1_TARGET__MASK				0x00000003
337 #define GEN75_BT_EDIT_DW1_TARGET__SHIFT				0
338 #define GEN75_BT_EDIT_DW1_TARGET_CORE0				0x1
339 #define GEN75_BT_EDIT_DW1_TARGET_CORE1				0x2
340 #define GEN75_BT_EDIT_DW1_TARGET_ALL				0x3
341 
342 #define GEN75_BT_EDIT_DW_ENTRY_BT_INDEX__MASK			0x00ff0000
343 #define GEN75_BT_EDIT_DW_ENTRY_BT_INDEX__SHIFT			16
344 #define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__MASK		0x0000ffff
345 #define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHIFT	0
346 #define GEN75_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHR		5
347 #define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__MASK		0x0000ffff
348 #define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHIFT		0
349 #define GEN8_BT_EDIT_DW_ENTRY_SURFACE_STATE_ADDR__SHR		6
350 
351 #define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_ANY__SIZE		2
352 
353 
354 #define GEN7_PCB_ALLOC_DW1_OFFSET__MASK				0x000f0000
355 #define GEN7_PCB_ALLOC_DW1_OFFSET__SHIFT			16
356 #define GEN7_PCB_ALLOC_DW1_SIZE__MASK				0x0000001f
357 #define GEN7_PCB_ALLOC_DW1_SIZE__SHIFT				0
358 
359 #define GEN75_PCB_ALLOC_DW1_OFFSET__MASK			0x001f0000
360 #define GEN75_PCB_ALLOC_DW1_OFFSET__SHIFT			16
361 #define GEN75_PCB_ALLOC_DW1_SIZE__MASK				0x0000003f
362 #define GEN75_PCB_ALLOC_DW1_SIZE__SHIFT				0
363 
364 #define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC__SIZE		3
365 
366 
367 #define GEN75_BT_POOL_ALLOC_DW1_ADDR__MASK			0xfffff000
368 #define GEN75_BT_POOL_ALLOC_DW1_ADDR__SHIFT			12
369 #define GEN75_BT_POOL_ALLOC_DW1_ADDR__SHR			12
370 #define GEN75_BT_POOL_ALLOC_DW1_ENABLE				(0x1 << 11)
371 #define GEN75_BT_POOL_ALLOC_DW1_MOCS__MASK			0x00000780
372 #define GEN75_BT_POOL_ALLOC_DW1_MOCS__SHIFT			7
373 #define GEN8_BT_POOL_ALLOC_DW1_MOCS__MASK			0x0000007f
374 #define GEN8_BT_POOL_ALLOC_DW1_MOCS__SHIFT			0
375 
376 #define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__MASK			0xfffff000
377 #define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__SHIFT			12
378 #define GEN75_BT_POOL_ALLOC_DW2_END_ADDR__SHR			12
379 
380 
381 #define GEN8_BT_POOL_ALLOC_DW3_SIZE__MASK			0xfffff000
382 #define GEN8_BT_POOL_ALLOC_DW3_SIZE__SHIFT			12
383 #define GEN8_BT_POOL_ALLOC_DW3_SIZE__SHR			12
384 
385 #define GEN75_3DSTATE_GATHER_POOL_ALLOC__SIZE			3
386 
387 
388 #define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__MASK			0xfffff000
389 #define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__SHIFT			12
390 #define GEN75_GATHER_POOL_ALLOC_DW1_ADDR__SHR			12
391 #define GEN75_GATHER_POOL_ALLOC_DW1_ENABLE			(0x1 << 11)
392 #define GEN75_GATHER_POOL_ALLOC_DW1_MOCS__MASK			0x0000000f
393 #define GEN75_GATHER_POOL_ALLOC_DW1_MOCS__SHIFT			0
394 #define GEN8_GATHER_POOL_ALLOC_DW1_MOCS__MASK			0x0000007f
395 #define GEN8_GATHER_POOL_ALLOC_DW1_MOCS__SHIFT			0
396 
397 #define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__MASK		0xfffff000
398 #define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__SHIFT		12
399 #define GEN75_GATHER_POOL_ALLOC_DW2_END_ADDR__SHR		12
400 
401 
402 #define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__MASK			0xfffff000
403 #define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__SHIFT			12
404 #define GEN8_GATHER_POOL_ALLOC_DW3_SIZE__SHR			12
405 
406 #define GEN6_3DSTATE_VERTEX_BUFFERS__SIZE			133
407 
408 
409 
410 #define GEN6_VB_DW0_INDEX__MASK					0xfc000000
411 #define GEN6_VB_DW0_INDEX__SHIFT				26
412 #define GEN8_VB_DW0_MOCS__MASK					0x007f0000
413 #define GEN8_VB_DW0_MOCS__SHIFT					16
414 #define GEN6_VB_DW0_ACCESS__MASK				0x00100000
415 #define GEN6_VB_DW0_ACCESS__SHIFT				20
416 #define GEN6_VB_DW0_ACCESS_VERTEXDATA				(0x0 << 20)
417 #define GEN6_VB_DW0_ACCESS_INSTANCEDATA				(0x1 << 20)
418 #define GEN6_VB_DW0_MOCS__MASK					0x000f0000
419 #define GEN6_VB_DW0_MOCS__SHIFT					16
420 #define GEN7_VB_DW0_ADDR_MODIFIED				(0x1 << 14)
421 #define GEN6_VB_DW0_IS_NULL					(0x1 << 13)
422 #define GEN6_VB_DW0_CACHE_INVALIDATE				(0x1 << 12)
423 #define GEN6_VB_DW0_PITCH__MASK					0x00000fff
424 #define GEN6_VB_DW0_PITCH__SHIFT				0
425 
426 
427 
428 
429 
430 
431 
432 #define GEN6_3DSTATE_VERTEX_ELEMENTS__SIZE			69
433 
434 
435 
436 #define GEN6_VE_DW0_VB_INDEX__MASK				0xfc000000
437 #define GEN6_VE_DW0_VB_INDEX__SHIFT				26
438 #define GEN6_VE_DW0_VALID					(0x1 << 25)
439 #define GEN6_VE_DW0_FORMAT__MASK				0x01ff0000
440 #define GEN6_VE_DW0_FORMAT__SHIFT				16
441 #define GEN6_VE_DW0_EDGE_FLAG_ENABLE				(0x1 << 15)
442 #define GEN6_VE_DW0_VB_OFFSET__MASK				0x000007ff
443 #define GEN6_VE_DW0_VB_OFFSET__SHIFT				0
444 #define GEN75_VE_DW0_VB_OFFSET__MASK				0x00000fff
445 #define GEN75_VE_DW0_VB_OFFSET__SHIFT				0
446 
447 #define GEN6_VE_DW1_COMP0__MASK					0x70000000
448 #define GEN6_VE_DW1_COMP0__SHIFT				28
449 #define GEN6_VE_DW1_COMP1__MASK					0x07000000
450 #define GEN6_VE_DW1_COMP1__SHIFT				24
451 #define GEN6_VE_DW1_COMP2__MASK					0x00700000
452 #define GEN6_VE_DW1_COMP2__SHIFT				20
453 #define GEN6_VE_DW1_COMP3__MASK					0x00070000
454 #define GEN6_VE_DW1_COMP3__SHIFT				16
455 
456 #define GEN6_3DSTATE_INDEX_BUFFER__SIZE				5
457 
458 #define GEN6_IB_DW0_MOCS__MASK					0x0000f000
459 #define GEN6_IB_DW0_MOCS__SHIFT					12
460 #define GEN6_IB_DW0_CUT_INDEX_ENABLE				(0x1 << 10)
461 #define GEN6_IB_DW0_FORMAT__MASK				0x00000300
462 #define GEN6_IB_DW0_FORMAT__SHIFT				8
463 
464 
465 
466 
467 
468 #define GEN8_IB_DW1_FORMAT__MASK				0x00000300
469 #define GEN8_IB_DW1_FORMAT__SHIFT				8
470 #define GEN8_IB_DW1_MOCS__MASK					0x0000007f
471 #define GEN8_IB_DW1_MOCS__SHIFT					0
472 
473 
474 
475 
476 #define GEN75_3DSTATE_VF__SIZE					2
477 
478 #define GEN75_VF_DW0_CUT_INDEX_ENABLE				(0x1 << 8)
479 
480 
481 #define GEN8_3DSTATE_VF_INSTANCING__SIZE			3
482 
483 
484 #define GEN8_INSTANCING_DW1_ENABLE				(0x1 << 8)
485 #define GEN8_INSTANCING_DW1_VE_INDEX__MASK			0x0000003f
486 #define GEN8_INSTANCING_DW1_VE_INDEX__SHIFT			0
487 
488 
489 #define GEN8_3DSTATE_VF_SGVS__SIZE				2
490 
491 
492 #define GEN8_SGVS_DW1_IID_ENABLE				(0x1 << 31)
493 #define GEN8_SGVS_DW1_IID_COMP__MASK				0x60000000
494 #define GEN8_SGVS_DW1_IID_COMP__SHIFT				29
495 #define GEN8_SGVS_DW1_IID_OFFSET__MASK				0x003f0000
496 #define GEN8_SGVS_DW1_IID_OFFSET__SHIFT				16
497 #define GEN8_SGVS_DW1_VID_ENABLE				(0x1 << 15)
498 #define GEN8_SGVS_DW1_VID_COMP__MASK				0x00006000
499 #define GEN8_SGVS_DW1_VID_COMP__SHIFT				13
500 #define GEN8_SGVS_DW1_VID_OFFSET__MASK				0x0000003f
501 #define GEN8_SGVS_DW1_VID_OFFSET__SHIFT				0
502 
503 #define GEN8_3DSTATE_VF_TOPOLOGY__SIZE				2
504 
505 
506 #define GEN8_TOPOLOGY_DW1_TYPE__MASK				0x0000003f
507 #define GEN8_TOPOLOGY_DW1_TYPE__SHIFT				0
508 
509 #define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS__SIZE		4
510 
511 #define GEN6_VP_PTR_DW0_CC_CHANGED				(0x1 << 12)
512 #define GEN6_VP_PTR_DW0_SF_CHANGED				(0x1 << 11)
513 #define GEN6_VP_PTR_DW0_CLIP_CHANGED				(0x1 << 10)
514 
515 #define GEN6_VP_PTR_DW1_CLIP_ADDR__MASK				0xffffffe0
516 #define GEN6_VP_PTR_DW1_CLIP_ADDR__SHIFT			5
517 #define GEN6_VP_PTR_DW1_CLIP_ADDR__SHR				5
518 
519 #define GEN6_VP_PTR_DW2_SF_ADDR__MASK				0xffffffe0
520 #define GEN6_VP_PTR_DW2_SF_ADDR__SHIFT				5
521 #define GEN6_VP_PTR_DW2_SF_ADDR__SHR				5
522 
523 #define GEN6_VP_PTR_DW3_CC_ADDR__MASK				0xffffffe0
524 #define GEN6_VP_PTR_DW3_CC_ADDR__SHIFT				5
525 #define GEN6_VP_PTR_DW3_CC_ADDR__SHR				5
526 
527 #define GEN6_3DSTATE_CC_STATE_POINTERS__SIZE			4
528 
529 
530 #define GEN6_CC_PTR_DW1_BLEND_CHANGED				(0x1 << 0)
531 #define GEN6_CC_PTR_DW1_BLEND_ADDR__MASK			0xffffffc0
532 #define GEN6_CC_PTR_DW1_BLEND_ADDR__SHIFT			6
533 #define GEN6_CC_PTR_DW1_BLEND_ADDR__SHR				6
534 
535 #define GEN6_CC_PTR_DW2_ZS_CHANGED				(0x1 << 0)
536 #define GEN6_CC_PTR_DW2_ZS_ADDR__MASK				0xffffffc0
537 #define GEN6_CC_PTR_DW2_ZS_ADDR__SHIFT				6
538 #define GEN6_CC_PTR_DW2_ZS_ADDR__SHR				6
539 
540 #define GEN6_CC_PTR_DW3_CC_CHANGED				(0x1 << 0)
541 #define GEN6_CC_PTR_DW3_CC_ADDR__MASK				0xffffffc0
542 #define GEN6_CC_PTR_DW3_CC_ADDR__SHIFT				6
543 #define GEN6_CC_PTR_DW3_CC_ADDR__SHR				6
544 
545 #define GEN6_3DSTATE_SCISSOR_STATE_POINTERS__SIZE		2
546 
547 
548 #define GEN6_SCISSOR_PTR_DW1_ADDR__MASK				0xffffffe0
549 #define GEN6_SCISSOR_PTR_DW1_ADDR__SHIFT			5
550 #define GEN6_SCISSOR_PTR_DW1_ADDR__SHR				5
551 
552 #define GEN7_3DSTATE_POINTERS_ANY__SIZE				2
553 
554 
555 #define GEN7_PTR_DW1_ADDR__MASK					0xffffffe0
556 #define GEN7_PTR_DW1_ADDR__SHIFT				5
557 #define GEN7_PTR_DW1_ADDR__SHR					5
558 #define GEN8_PTR_DW1_CHANGED					(0x1 << 0)
559 
560 #define GEN6_3DSTATE_VS__SIZE					9
561 
562 
563 #define GEN6_VS_DW1_KERNEL_ADDR__MASK				0xffffffc0
564 #define GEN6_VS_DW1_KERNEL_ADDR__SHIFT				6
565 #define GEN6_VS_DW1_KERNEL_ADDR__SHR				6
566 
567 
568 
569 #define GEN6_VS_DW4_URB_GRF_START__MASK				0x01f00000
570 #define GEN6_VS_DW4_URB_GRF_START__SHIFT			20
571 #define GEN6_VS_DW4_URB_READ_LEN__MASK				0x0001f800
572 #define GEN6_VS_DW4_URB_READ_LEN__SHIFT				11
573 #define GEN6_VS_DW4_URB_READ_OFFSET__MASK			0x000003f0
574 #define GEN6_VS_DW4_URB_READ_OFFSET__SHIFT			4
575 
576 #define GEN6_VS_DW5_MAX_THREADS__MASK				0xfe000000
577 #define GEN6_VS_DW5_MAX_THREADS__SHIFT				25
578 #define GEN75_VS_DW5_MAX_THREADS__MASK				0xff800000
579 #define GEN75_VS_DW5_MAX_THREADS__SHIFT				23
580 #define GEN6_VS_DW5_STATISTICS					(0x1 << 10)
581 #define GEN6_VS_DW5_CACHE_DISABLE				(0x1 << 1)
582 #define GEN6_VS_DW5_VS_ENABLE					(0x1 << 0)
583 
584 
585 
586 #define GEN8_VS_DW1_KERNEL_ADDR__MASK				0xffffffc0
587 #define GEN8_VS_DW1_KERNEL_ADDR__SHIFT				6
588 #define GEN8_VS_DW1_KERNEL_ADDR__SHR				6
589 
590 
591 
592 
593 
594 #define GEN8_VS_DW6_URB_GRF_START__MASK				0x01f00000
595 #define GEN8_VS_DW6_URB_GRF_START__SHIFT			20
596 #define GEN8_VS_DW6_URB_READ_LEN__MASK				0x0001f800
597 #define GEN8_VS_DW6_URB_READ_LEN__SHIFT				11
598 #define GEN8_VS_DW6_URB_READ_OFFSET__MASK			0x000003f0
599 #define GEN8_VS_DW6_URB_READ_OFFSET__SHIFT			4
600 
601 #define GEN8_VS_DW7_MAX_THREADS__MASK				0xff800000
602 #define GEN8_VS_DW7_MAX_THREADS__SHIFT				23
603 #define GEN8_VS_DW7_STATISTICS					(0x1 << 10)
604 #define GEN8_VS_DW7_SIMD8_ENABLE				(0x1 << 2)
605 #define GEN8_VS_DW7_CACHE_DISABLE				(0x1 << 1)
606 #define GEN8_VS_DW7_VS_ENABLE					(0x1 << 0)
607 
608 #define GEN8_VS_DW8_VUE_OUT_READ_OFFSET__MASK			0x07e00000
609 #define GEN8_VS_DW8_VUE_OUT_READ_OFFSET__SHIFT			21
610 #define GEN8_VS_DW8_VUE_OUT_LEN__MASK				0x001f0000
611 #define GEN8_VS_DW8_VUE_OUT_LEN__SHIFT				16
612 #define GEN8_VS_DW8_UCP_CLIP_ENABLES__MASK			0x0000ff00
613 #define GEN8_VS_DW8_UCP_CLIP_ENABLES__SHIFT			8
614 #define GEN8_VS_DW8_UCP_CULL_ENABLES__MASK			0x000000ff
615 #define GEN8_VS_DW8_UCP_CULL_ENABLES__SHIFT			0
616 
617 #define GEN7_3DSTATE_HS__SIZE					9
618 
619 
620 #define GEN7_HS_DW1_DISPATCH_MAX_THREADS__MASK			0x0000007f
621 #define GEN7_HS_DW1_DISPATCH_MAX_THREADS__SHIFT			0
622 #define GEN75_HS_DW1_DISPATCH_MAX_THREADS__MASK			0x000000ff
623 #define GEN75_HS_DW1_DISPATCH_MAX_THREADS__SHIFT		0
624 
625 #define GEN7_HS_DW2_HS_ENABLE					(0x1 << 31)
626 #define GEN7_HS_DW2_STATISTICS					(0x1 << 29)
627 #define GEN7_HS_DW2_INSTANCE_COUNT__MASK			0x0000000f
628 #define GEN7_HS_DW2_INSTANCE_COUNT__SHIFT			0
629 
630 #define GEN7_HS_DW3_KERNEL_ADDR__MASK				0xffffffc0
631 #define GEN7_HS_DW3_KERNEL_ADDR__SHIFT				6
632 #define GEN7_HS_DW3_KERNEL_ADDR__SHR				6
633 
634 
635 #define GEN7_HS_DW5_SPF						(0x1 << 27)
636 #define GEN7_HS_DW5_VME						(0x1 << 26)
637 #define GEN75_HS_DW5_ACCESS_UAV					(0x1 << 25)
638 #define GEN7_HS_DW5_INCLUDE_VERTEX_HANDLES			(0x1 << 24)
639 #define GEN7_HS_DW5_URB_GRF_START__MASK				0x00f80000
640 #define GEN7_HS_DW5_URB_GRF_START__SHIFT			19
641 #define GEN7_HS_DW5_URB_READ_LEN__MASK				0x0001f800
642 #define GEN7_HS_DW5_URB_READ_LEN__SHIFT				11
643 #define GEN7_HS_DW5_URB_READ_OFFSET__MASK			0x000003f0
644 #define GEN7_HS_DW5_URB_READ_OFFSET__SHIFT			4
645 
646 #define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__MASK			0x00000fff
647 #define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__SHIFT			0
648 #define GEN7_HS_DW6_URB_SEMAPHORE_ADDR__SHR			6
649 #define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__MASK			0x00001fff
650 #define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHIFT			0
651 #define GEN75_HS_DW6_URB_SEMAPHORE_ADDR__SHR			6
652 
653 
654 
655 
656 #define GEN8_HS_DW2_HS_ENABLE					(0x1 << 31)
657 #define GEN8_HS_DW2_STATISTICS					(0x1 << 29)
658 #define GEN8_HS_DW2_MAX_THREADS__MASK				0x0001ff00
659 #define GEN8_HS_DW2_MAX_THREADS__SHIFT				8
660 #define GEN8_HS_DW2_INSTANCE_COUNT__MASK			0x0000000f
661 #define GEN8_HS_DW2_INSTANCE_COUNT__SHIFT			0
662 
663 #define GEN8_HS_DW3_KERNEL_ADDR__MASK				0xffffffc0
664 #define GEN8_HS_DW3_KERNEL_ADDR__SHIFT				6
665 #define GEN8_HS_DW3_KERNEL_ADDR__SHR				6
666 
667 
668 
669 
670 #define GEN8_HS_DW7_SPF						(0x1 << 27)
671 #define GEN8_HS_DW7_VME						(0x1 << 26)
672 #define GEN8_HS_DW7_ACCESS_UAV					(0x1 << 25)
673 #define GEN8_HS_DW7_INCLUDE_VERTEX_HANDLES			(0x1 << 24)
674 #define GEN8_HS_DW7_URB_GRF_START__MASK				0x00f80000
675 #define GEN8_HS_DW7_URB_GRF_START__SHIFT			19
676 #define GEN8_HS_DW7_URB_READ_LEN__MASK				0x0001f800
677 #define GEN8_HS_DW7_URB_READ_LEN__SHIFT				11
678 #define GEN8_HS_DW7_URB_READ_OFFSET__MASK			0x000003f0
679 #define GEN8_HS_DW7_URB_READ_OFFSET__SHIFT			4
680 
681 
682 #define GEN7_3DSTATE_TE__SIZE					4
683 
684 
685 #define GEN7_TE_DW1_PARTITIONING__MASK				0x00003000
686 #define GEN7_TE_DW1_PARTITIONING__SHIFT				12
687 #define GEN7_TE_DW1_PARTITIONING_INTEGER			(0x0 << 12)
688 #define GEN7_TE_DW1_PARTITIONING_ODD_FRACTIONAL			(0x1 << 12)
689 #define GEN7_TE_DW1_PARTITIONING_EVEN_FRACTIONAL		(0x2 << 12)
690 #define GEN7_TE_DW1_OUTPUT_TOPO__MASK				0x00000300
691 #define GEN7_TE_DW1_OUTPUT_TOPO__SHIFT				8
692 #define GEN7_TE_DW1_OUTPUT_TOPO_POINT				(0x0 << 8)
693 #define GEN7_TE_DW1_OUTPUT_TOPO_LINE				(0x1 << 8)
694 #define GEN7_TE_DW1_OUTPUT_TOPO_TRI_CW				(0x2 << 8)
695 #define GEN7_TE_DW1_OUTPUT_TOPO_TRI_CCW				(0x3 << 8)
696 #define GEN7_TE_DW1_DOMAIN__MASK				0x00000030
697 #define GEN7_TE_DW1_DOMAIN__SHIFT				4
698 #define GEN7_TE_DW1_DOMAIN_QUAD					(0x0 << 4)
699 #define GEN7_TE_DW1_DOMAIN_TRI					(0x1 << 4)
700 #define GEN7_TE_DW1_DOMAIN_ISOLINE				(0x2 << 4)
701 #define GEN7_TE_DW1_MODE__MASK					0x00000006
702 #define GEN7_TE_DW1_MODE__SHIFT					1
703 #define GEN7_TE_DW1_MODE_HW					(0x0 << 1)
704 #define GEN7_TE_DW1_MODE_SW					(0x1 << 1)
705 #define GEN7_TE_DW1_TE_ENABLE					(0x1 << 0)
706 
707 
708 
709 #define GEN7_3DSTATE_DS__SIZE					11
710 
711 
712 #define GEN7_DS_DW1_KERNEL_ADDR__MASK				0xffffffc0
713 #define GEN7_DS_DW1_KERNEL_ADDR__SHIFT				6
714 #define GEN7_DS_DW1_KERNEL_ADDR__SHR				6
715 
716 
717 
718 #define GEN7_DS_DW4_URB_GRF_START__MASK				0x01f00000
719 #define GEN7_DS_DW4_URB_GRF_START__SHIFT			20
720 #define GEN7_DS_DW4_URB_READ_LEN__MASK				0x0003f800
721 #define GEN7_DS_DW4_URB_READ_LEN__SHIFT				11
722 #define GEN7_DS_DW4_URB_READ_OFFSET__MASK			0x000003f0
723 #define GEN7_DS_DW4_URB_READ_OFFSET__SHIFT			4
724 
725 #define GEN7_DS_DW5_MAX_THREADS__MASK				0xfe000000
726 #define GEN7_DS_DW5_MAX_THREADS__SHIFT				25
727 #define GEN75_DS_DW5_MAX_THREADS__MASK				0x3fe00000
728 #define GEN75_DS_DW5_MAX_THREADS__SHIFT				21
729 #define GEN7_DS_DW5_STATISTICS					(0x1 << 10)
730 #define GEN7_DS_DW5_COMPUTE_W					(0x1 << 2)
731 #define GEN7_DS_DW5_CACHE_DISABLE				(0x1 << 1)
732 #define GEN7_DS_DW5_DS_ENABLE					(0x1 << 0)
733 
734 
735 
736 #define GEN8_DS_DW1_KERNEL_ADDR__MASK				0xffffffc0
737 #define GEN8_DS_DW1_KERNEL_ADDR__SHIFT				6
738 #define GEN8_DS_DW1_KERNEL_ADDR__SHR				6
739 
740 
741 
742 
743 
744 #define GEN8_DS_DW6_URB_GRF_START__MASK				0x01f00000
745 #define GEN8_DS_DW6_URB_GRF_START__SHIFT			20
746 #define GEN8_DS_DW6_URB_READ_LEN__MASK				0x0003f800
747 #define GEN8_DS_DW6_URB_READ_LEN__SHIFT				11
748 #define GEN8_DS_DW6_URB_READ_OFFSET__MASK			0x000003f0
749 #define GEN8_DS_DW6_URB_READ_OFFSET__SHIFT			4
750 
751 #define GEN8_DS_DW7_MAX_THREADS__MASK				0x3fe00000
752 #define GEN8_DS_DW7_MAX_THREADS__SHIFT				21
753 #define GEN8_DS_DW7_STATISTICS					(0x1 << 10)
754 #define GEN8_DS_DW7_SIMD8_ENABLE				(0x1 << 3)
755 #define GEN8_DS_DW7_COMPUTE_W					(0x1 << 2)
756 #define GEN8_DS_DW7_CACHE_DISABLE				(0x1 << 1)
757 #define GEN8_DS_DW7_DS_ENABLE					(0x1 << 0)
758 
759 #define GEN8_DS_DW8_VUE_OUT_READ_OFFSET__MASK			0x07e00000
760 #define GEN8_DS_DW8_VUE_OUT_READ_OFFSET__SHIFT			21
761 #define GEN8_DS_DW8_VUE_OUT_LEN__MASK				0x001f0000
762 #define GEN8_DS_DW8_VUE_OUT_LEN__SHIFT				16
763 #define GEN8_DS_DW8_UCP_CLIP_ENABLES__MASK			0x0000ff00
764 #define GEN8_DS_DW8_UCP_CLIP_ENABLES__SHIFT			8
765 #define GEN8_DS_DW8_UCP_CULL_ENABLES__MASK			0x000000ff
766 #define GEN8_DS_DW8_UCP_CULL_ENABLES__SHIFT			0
767 
768 
769 
770 #define GEN6_3DSTATE_GS__SIZE					10
771 
772 
773 #define GEN6_GS_DW1_KERNEL_ADDR__MASK				0xffffffc0
774 #define GEN6_GS_DW1_KERNEL_ADDR__SHIFT				6
775 #define GEN6_GS_DW1_KERNEL_ADDR__SHR				6
776 
777 
778 
779 #define GEN6_GS_DW4_URB_READ_LEN__MASK				0x0001f800
780 #define GEN6_GS_DW4_URB_READ_LEN__SHIFT				11
781 #define GEN6_GS_DW4_URB_READ_OFFSET__MASK			0x000003f0
782 #define GEN6_GS_DW4_URB_READ_OFFSET__SHIFT			4
783 #define GEN6_GS_DW4_URB_GRF_START__MASK				0x0000000f
784 #define GEN6_GS_DW4_URB_GRF_START__SHIFT			0
785 
786 #define GEN6_GS_DW5_MAX_THREADS__MASK				0xfe000000
787 #define GEN6_GS_DW5_MAX_THREADS__SHIFT				25
788 #define GEN6_GS_DW5_STATISTICS					(0x1 << 10)
789 #define GEN6_GS_DW5_SO_STATISTICS				(0x1 << 9)
790 #define GEN6_GS_DW5_RENDER_ENABLE				(0x1 << 8)
791 
792 #define GEN6_GS_DW6_REORDER_LEADING_ENABLE			(0x1 << 30)
793 #define GEN6_GS_DW6_DISCARD_ADJACENCY				(0x1 << 29)
794 #define GEN6_GS_DW6_SVBI_PAYLOAD_ENABLE				(0x1 << 28)
795 #define GEN6_GS_DW6_SVBI_POST_INC_ENABLE			(0x1 << 27)
796 #define GEN6_GS_DW6_SVBI_POST_INC_VAL__MASK			0x03ff0000
797 #define GEN6_GS_DW6_SVBI_POST_INC_VAL__SHIFT			16
798 #define GEN6_GS_DW6_GS_ENABLE					(0x1 << 15)
799 
800 
801 
802 #define GEN7_GS_DW1_KERNEL_ADDR__MASK				0xffffffc0
803 #define GEN7_GS_DW1_KERNEL_ADDR__SHIFT				6
804 #define GEN7_GS_DW1_KERNEL_ADDR__SHR				6
805 
806 
807 
808 #define GEN7_GS_DW4_OUTPUT_SIZE__MASK				0x1f800000
809 #define GEN7_GS_DW4_OUTPUT_SIZE__SHIFT				23
810 #define GEN7_GS_DW4_OUTPUT_TOPO__MASK				0x007e0000
811 #define GEN7_GS_DW4_OUTPUT_TOPO__SHIFT				17
812 #define GEN7_GS_DW4_URB_READ_LEN__MASK				0x0001f800
813 #define GEN7_GS_DW4_URB_READ_LEN__SHIFT				11
814 #define GEN7_GS_DW4_INCLUDE_VERTEX_HANDLES			(0x1 << 10)
815 #define GEN7_GS_DW4_URB_READ_OFFSET__MASK			0x000003f0
816 #define GEN7_GS_DW4_URB_READ_OFFSET__SHIFT			4
817 #define GEN7_GS_DW4_URB_GRF_START__MASK				0x0000000f
818 #define GEN7_GS_DW4_URB_GRF_START__SHIFT			0
819 
820 #define GEN7_GS_DW5_MAX_THREADS__MASK				0xfe000000
821 #define GEN7_GS_DW5_MAX_THREADS__SHIFT				25
822 #define GEN7_GS_DW5_GSCTRL__MASK				0x01000000
823 #define GEN7_GS_DW5_GSCTRL__SHIFT				24
824 #define GEN7_GS_DW5_GSCTRL_CUT					(0x0 << 24)
825 #define GEN7_GS_DW5_GSCTRL_SID					(0x1 << 24)
826 #define GEN75_GS_DW5_MAX_THREADS__MASK				0xff000000
827 #define GEN75_GS_DW5_MAX_THREADS__SHIFT				24
828 #define GEN7_GS_DW5_CONTROL_DATA_HEADER_SIZE__MASK		0x00f00000
829 #define GEN7_GS_DW5_CONTROL_DATA_HEADER_SIZE__SHIFT		20
830 #define GEN7_GS_DW5_INSTANCE_CONTROL__MASK			0x000f8000
831 #define GEN7_GS_DW5_INSTANCE_CONTROL__SHIFT			15
832 #define GEN7_GS_DW5_DEFAULT_STREAM_ID__MASK			0x00006000
833 #define GEN7_GS_DW5_DEFAULT_STREAM_ID__SHIFT			13
834 #define GEN7_GS_DW5_DISPATCH_MODE__MASK				0x00001800
835 #define GEN7_GS_DW5_DISPATCH_MODE__SHIFT			11
836 #define GEN7_GS_DW5_DISPATCH_MODE_SINGLE			(0x0 << 11)
837 #define GEN7_GS_DW5_DISPATCH_MODE_DUAL_INSTANCE			(0x1 << 11)
838 #define GEN7_GS_DW5_DISPATCH_MODE_DUAL_OBJECT			(0x2 << 11)
839 #define GEN7_GS_DW5_STATISTICS					(0x1 << 10)
840 #define GEN7_GS_DW5_INVOCATION_INCR__MASK			0x000003e0
841 #define GEN7_GS_DW5_INVOCATION_INCR__SHIFT			5
842 #define GEN7_GS_DW5_INCLUDE_PRIMITIVE_ID			(0x1 << 4)
843 #define GEN7_GS_DW5_HINT					(0x1 << 3)
844 #define GEN7_GS_DW5_REORDER_LEADING_ENABLE			(0x1 << 2)
845 #define GEN75_GS_DW5_REORDER_MODE__MASK				0x00000004
846 #define GEN75_GS_DW5_REORDER_MODE__SHIFT			2
847 #define GEN7_GS_DW5_DISCARD_ADJACENCY				(0x1 << 1)
848 #define GEN7_GS_DW5_GS_ENABLE					(0x1 << 0)
849 
850 #define GEN75_GS_DW6_GSCTRL__MASK				0x80000000
851 #define GEN75_GS_DW6_GSCTRL__SHIFT				31
852 #define GEN75_GS_DW6_GSCTRL_CUT					(0x0 << 31)
853 #define GEN75_GS_DW6_GSCTRL_SID					(0x1 << 31)
854 #define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__MASK			0x00000fff
855 #define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__SHIFT			0
856 #define GEN7_GS_DW6_URB_SEMAPHORE_ADDR__SHR			6
857 #define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__MASK			0x00001fff
858 #define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHIFT			0
859 #define GEN75_GS_DW6_URB_SEMAPHORE_ADDR__SHR			6
860 
861 
862 
863 #define GEN8_GS_DW1_KERNEL_ADDR__MASK				0xffffffc0
864 #define GEN8_GS_DW1_KERNEL_ADDR__SHIFT				6
865 #define GEN8_GS_DW1_KERNEL_ADDR__SHR				6
866 
867 
868 #define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__MASK			0x0000003f
869 #define GEN8_GS_DW3_EXPECTED_VERTEX_COUNT__SHIFT		0
870 
871 
872 
873 #define GEN8_GS_DW6_OUTPUT_SIZE__MASK				0x1f800000
874 #define GEN8_GS_DW6_OUTPUT_SIZE__SHIFT				23
875 #define GEN8_GS_DW6_OUTPUT_TOPO__MASK				0x007e0000
876 #define GEN8_GS_DW6_OUTPUT_TOPO__SHIFT				17
877 #define GEN8_GS_DW6_URB_READ_LEN__MASK				0x0001f800
878 #define GEN8_GS_DW6_URB_READ_LEN__SHIFT				11
879 #define GEN8_GS_DW6_INCLUDE_VERTEX_HANDLES			(0x1 << 10)
880 #define GEN8_GS_DW6_URB_READ_OFFSET__MASK			0x000003f0
881 #define GEN8_GS_DW6_URB_READ_OFFSET__SHIFT			4
882 #define GEN8_GS_DW6_URB_GRF_START__MASK				0x0000000f
883 #define GEN8_GS_DW6_URB_GRF_START__SHIFT			0
884 
885 #define GEN8_GS_DW7_MAX_THREADS__MASK				0xff000000
886 #define GEN8_GS_DW7_MAX_THREADS__SHIFT				24
887 #define GEN8_GS_DW7_CONTROL_DATA_HEADER_SIZE__MASK		0x00f00000
888 #define GEN8_GS_DW7_CONTROL_DATA_HEADER_SIZE__SHIFT		20
889 #define GEN8_GS_DW7_INSTANCE_CONTROL__MASK			0x000f8000
890 #define GEN8_GS_DW7_INSTANCE_CONTROL__SHIFT			15
891 #define GEN8_GS_DW7_DEFAULT_STREAM_ID__MASK			0x00006000
892 #define GEN8_GS_DW7_DEFAULT_STREAM_ID__SHIFT			13
893 #define GEN8_GS_DW7_DISPATCH_MODE__MASK				0x00001800
894 #define GEN8_GS_DW7_DISPATCH_MODE__SHIFT			11
895 #define GEN8_GS_DW7_DISPATCH_MODE_SINGLE			(0x0 << 11)
896 #define GEN8_GS_DW7_DISPATCH_MODE_DUAL_INSTANCE			(0x1 << 11)
897 #define GEN8_GS_DW7_DISPATCH_MODE_DUAL_OBJECT			(0x2 << 11)
898 #define GEN8_GS_DW7_STATISTICS					(0x1 << 10)
899 #define GEN8_GS_DW7_INVOCATION_INCR__MASK			0x000003e0
900 #define GEN8_GS_DW7_INVOCATION_INCR__SHIFT			5
901 #define GEN8_GS_DW7_INCLUDE_PRIMITIVE_ID			(0x1 << 4)
902 #define GEN8_GS_DW7_HINT					(0x1 << 3)
903 #define GEN8_GS_DW7_REORDER_MODE__MASK				0x00000004
904 #define GEN8_GS_DW7_REORDER_MODE__SHIFT				2
905 #define GEN8_GS_DW7_DISCARD_ADJACENCY				(0x1 << 1)
906 #define GEN8_GS_DW7_GS_ENABLE					(0x1 << 0)
907 
908 #define GEN8_GS_DW8_GSCTRL__MASK				0x80000000
909 #define GEN8_GS_DW8_GSCTRL__SHIFT				31
910 #define GEN8_GS_DW8_GSCTRL_CUT					(0x0 << 31)
911 #define GEN8_GS_DW8_GSCTRL_SID					(0x1 << 31)
912 #define GEN8_GS_DW8_STATIC_OUTPUT				(0x1 << 30)
913 #define GEN8_GS_DW8_STATIC_OUTPUT_VERTEX_COUNT__MASK		0x07ff0000
914 #define GEN8_GS_DW8_STATIC_OUTPUT_VERTEX_COUNT__SHIFT		16
915 #define GEN9_GS_DW8_MAX_THREADS__MASK				0x000001ff
916 #define GEN9_GS_DW8_MAX_THREADS__SHIFT				0
917 
918 #define GEN8_GS_DW9_VUE_OUT_READ_OFFSET__MASK			0x07e00000
919 #define GEN8_GS_DW9_VUE_OUT_READ_OFFSET__SHIFT			21
920 #define GEN8_GS_DW9_VUE_OUT_LEN__MASK				0x001f0000
921 #define GEN8_GS_DW9_VUE_OUT_LEN__SHIFT				16
922 #define GEN8_GS_DW9_UCP_CLIP_ENABLES__MASK			0x0000ff00
923 #define GEN8_GS_DW9_UCP_CLIP_ENABLES__SHIFT			8
924 #define GEN8_GS_DW9_UCP_CULL_ENABLES__MASK			0x000000ff
925 #define GEN8_GS_DW9_UCP_CULL_ENABLES__SHIFT			0
926 
927 #define GEN7_3DSTATE_STREAMOUT__SIZE				5
928 
929 
930 #define GEN7_SO_DW1_SO_ENABLE					(0x1 << 31)
931 #define GEN7_SO_DW1_RENDER_DISABLE				(0x1 << 30)
932 #define GEN7_SO_DW1_RENDER_STREAM_SELECT__MASK			0x18000000
933 #define GEN7_SO_DW1_RENDER_STREAM_SELECT__SHIFT			27
934 #define GEN7_SO_DW1_REORDER_MODE__MASK				0x04000000
935 #define GEN7_SO_DW1_REORDER_MODE__SHIFT				26
936 #define GEN7_SO_DW1_STATISTICS					(0x1 << 25)
937 #define GEN8_SO_DW1_FORCE_RENDERING__MASK			0x01800000
938 #define GEN8_SO_DW1_FORCE_RENDERING__SHIFT			23
939 #define GEN8_SO_DW1_FORCE_RENDERING_NORMAL			(0x0 << 23)
940 #define GEN8_SO_DW1_FORCE_RENDERING_OFF				(0x2 << 23)
941 #define GEN8_SO_DW1_FORCE_RENDERING_ON				(0x3 << 23)
942 #define GEN7_SO_DW1_BUFFER_ENABLES__MASK			0x00000f00
943 #define GEN7_SO_DW1_BUFFER_ENABLES__SHIFT			8
944 
945 #define GEN7_SO_DW2_STREAM3_READ_OFFSET__MASK			0x20000000
946 #define GEN7_SO_DW2_STREAM3_READ_OFFSET__SHIFT			29
947 #define GEN7_SO_DW2_STREAM3_READ_LEN__MASK			0x1f000000
948 #define GEN7_SO_DW2_STREAM3_READ_LEN__SHIFT			24
949 #define GEN7_SO_DW2_STREAM2_READ_OFFSET__MASK			0x00200000
950 #define GEN7_SO_DW2_STREAM2_READ_OFFSET__SHIFT			21
951 #define GEN7_SO_DW2_STREAM2_READ_LEN__MASK			0x001f0000
952 #define GEN7_SO_DW2_STREAM2_READ_LEN__SHIFT			16
953 #define GEN7_SO_DW2_STREAM1_READ_OFFSET__MASK			0x00002000
954 #define GEN7_SO_DW2_STREAM1_READ_OFFSET__SHIFT			13
955 #define GEN7_SO_DW2_STREAM1_READ_LEN__MASK			0x00001f00
956 #define GEN7_SO_DW2_STREAM1_READ_LEN__SHIFT			8
957 #define GEN7_SO_DW2_STREAM0_READ_OFFSET__MASK			0x00000020
958 #define GEN7_SO_DW2_STREAM0_READ_OFFSET__SHIFT			5
959 #define GEN7_SO_DW2_STREAM0_READ_LEN__MASK			0x0000001f
960 #define GEN7_SO_DW2_STREAM0_READ_LEN__SHIFT			0
961 
962 #define GEN8_SO_DW3_BUFFER1_PITCH__MASK				0x0fff0000
963 #define GEN8_SO_DW3_BUFFER1_PITCH__SHIFT			16
964 #define GEN8_SO_DW3_BUFFER0_PITCH__MASK				0x00000fff
965 #define GEN8_SO_DW3_BUFFER0_PITCH__SHIFT			0
966 
967 #define GEN8_SO_DW4_BUFFER3_PITCH__MASK				0x0fff0000
968 #define GEN8_SO_DW4_BUFFER3_PITCH__SHIFT			16
969 #define GEN8_SO_DW4_BUFFER2_PITCH__MASK				0x00000fff
970 #define GEN8_SO_DW4_BUFFER2_PITCH__SHIFT			0
971 
972 #define GEN7_3DSTATE_SO_DECL_LIST__SIZE				259
973 
974 
975 #define GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__MASK		0x0000f000
976 #define GEN7_SO_DECL_DW1_STREAM3_BUFFER_SELECTS__SHIFT		12
977 #define GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__MASK		0x00000f00
978 #define GEN7_SO_DECL_DW1_STREAM2_BUFFER_SELECTS__SHIFT		8
979 #define GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__MASK		0x000000f0
980 #define GEN7_SO_DECL_DW1_STREAM1_BUFFER_SELECTS__SHIFT		4
981 #define GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__MASK		0x0000000f
982 #define GEN7_SO_DECL_DW1_STREAM0_BUFFER_SELECTS__SHIFT		0
983 
984 #define GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__MASK		0xff000000
985 #define GEN7_SO_DECL_DW2_STREAM3_ENTRY_COUNT__SHIFT		24
986 #define GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__MASK		0x00ff0000
987 #define GEN7_SO_DECL_DW2_STREAM2_ENTRY_COUNT__SHIFT		16
988 #define GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__MASK		0x0000ff00
989 #define GEN7_SO_DECL_DW2_STREAM1_ENTRY_COUNT__SHIFT		8
990 #define GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__MASK		0x000000ff
991 #define GEN7_SO_DECL_DW2_STREAM0_ENTRY_COUNT__SHIFT		0
992 
993 #define GEN7_SO_DECL_HIGH__MASK					0xffff0000
994 #define GEN7_SO_DECL_HIGH__SHIFT				16
995 #define GEN7_SO_DECL_OUTPUT_SLOT__MASK				0x00003000
996 #define GEN7_SO_DECL_OUTPUT_SLOT__SHIFT				12
997 #define GEN7_SO_DECL_HOLE_FLAG					(0x1 << 11)
998 #define GEN7_SO_DECL_REG_INDEX__MASK				0x000003f0
999 #define GEN7_SO_DECL_REG_INDEX__SHIFT				4
1000 #define GEN7_SO_DECL_COMPONENT_MASK__MASK			0x0000000f
1001 #define GEN7_SO_DECL_COMPONENT_MASK__SHIFT			0
1002 
1003 #define GEN7_3DSTATE_SO_BUFFER__SIZE				8
1004 
1005 
1006 #define GEN8_SO_BUF_DW1_ENABLE					(0x1 << 31)
1007 #define GEN7_SO_BUF_DW1_INDEX__MASK				0x60000000
1008 #define GEN7_SO_BUF_DW1_INDEX__SHIFT				29
1009 #define GEN7_SO_BUF_DW1_MOCS__MASK				0x1e000000
1010 #define GEN7_SO_BUF_DW1_MOCS__SHIFT				25
1011 #define GEN8_SO_BUF_DW1_MOCS__MASK				0x1fc00000
1012 #define GEN8_SO_BUF_DW1_MOCS__SHIFT				22
1013 #define GEN8_SO_BUF_DW1_OFFSET_WRITE_ENABLE			(0x1 << 21)
1014 #define GEN8_SO_BUF_DW1_OFFSET_ENABLE				(0x1 << 20)
1015 #define GEN7_SO_BUF_DW1_PITCH__MASK				0x00000fff
1016 #define GEN7_SO_BUF_DW1_PITCH__SHIFT				0
1017 
1018 #define GEN7_SO_BUF_DW2_START_ADDR__MASK			0xfffffffc
1019 #define GEN7_SO_BUF_DW2_START_ADDR__SHIFT			2
1020 #define GEN7_SO_BUF_DW2_START_ADDR__SHR				2
1021 
1022 #define GEN7_SO_BUF_DW3_END_ADDR__MASK				0xfffffffc
1023 #define GEN7_SO_BUF_DW3_END_ADDR__SHIFT				2
1024 #define GEN7_SO_BUF_DW3_END_ADDR__SHR				2
1025 
1026 #define GEN8_SO_BUF_DW2_ADDR__MASK				0xfffffffc
1027 #define GEN8_SO_BUF_DW2_ADDR__SHIFT				2
1028 #define GEN8_SO_BUF_DW2_ADDR__SHR				2
1029 
1030 
1031 
1032 #define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__MASK			0xfffffffc
1033 #define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__SHIFT			2
1034 #define GEN8_SO_BUF_DW5_OFFSET_ADDR_ADDR__SHR			2
1035 
1036 
1037 
1038 #define GEN6_3DSTATE_CLIP__SIZE					4
1039 
1040 
1041 #define GEN7_CLIP_DW1_FRONT_WINDING__MASK			0x00100000
1042 #define GEN7_CLIP_DW1_FRONT_WINDING__SHIFT			20
1043 #define GEN8_CLIP_DW1_FORCE_UCP_CULL_ENABLES			(0x1 << 20)
1044 #define GEN7_CLIP_DW1_SUBPIXEL__MASK				0x00080000
1045 #define GEN7_CLIP_DW1_SUBPIXEL__SHIFT				19
1046 #define GEN7_CLIP_DW1_SUBPIXEL_8BITS				(0x0 << 19)
1047 #define GEN7_CLIP_DW1_SUBPIXEL_4BITS				(0x1 << 19)
1048 #define GEN7_CLIP_DW1_EARLY_CULL_ENABLE				(0x1 << 18)
1049 #define GEN7_CLIP_DW1_CULL_MODE__MASK				0x00030000
1050 #define GEN7_CLIP_DW1_CULL_MODE__SHIFT				16
1051 #define GEN8_CLIP_DW1_FORCE_UCP_CLIP_ENABLES			(0x1 << 17)
1052 #define GEN8_CLIP_DW1_FORCE_CLIP_MODE				(0x1 << 16)
1053 #define GEN6_CLIP_DW1_STATISTICS				(0x1 << 10)
1054 #define GEN6_CLIP_DW1_UCP_CULL_ENABLES__MASK			0x000000ff
1055 #define GEN6_CLIP_DW1_UCP_CULL_ENABLES__SHIFT			0
1056 
1057 #define GEN6_CLIP_DW2_CLIP_ENABLE				(0x1 << 31)
1058 #define GEN6_CLIP_DW2_APIMODE__MASK				0x40000000
1059 #define GEN6_CLIP_DW2_APIMODE__SHIFT				30
1060 #define GEN6_CLIP_DW2_APIMODE_OGL				(0x0 << 30)
1061 #define GEN6_CLIP_DW2_APIMODE_D3D				(0x1 << 30)
1062 #define GEN6_CLIP_DW2_XY_TEST_ENABLE				(0x1 << 28)
1063 #define GEN6_CLIP_DW2_Z_TEST_ENABLE				(0x1 << 27)
1064 #define GEN6_CLIP_DW2_GB_TEST_ENABLE				(0x1 << 26)
1065 #define GEN6_CLIP_DW2_UCP_CLIP_ENABLES__MASK			0x00ff0000
1066 #define GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT			16
1067 #define GEN6_CLIP_DW2_CLIP_MODE__MASK				0x0000e000
1068 #define GEN6_CLIP_DW2_CLIP_MODE__SHIFT				13
1069 #define GEN6_CLIP_DW2_PERSPECTIVE_DIVIDE_DISABLE		(0x1 << 9)
1070 #define GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE		(0x1 << 8)
1071 #define GEN6_CLIP_DW2_TRI_PROVOKE__MASK				0x00000030
1072 #define GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT			4
1073 #define GEN6_CLIP_DW2_LINE_PROVOKE__MASK			0x0000000c
1074 #define GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT			2
1075 #define GEN6_CLIP_DW2_TRIFAN_PROVOKE__MASK			0x00000003
1076 #define GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT			0
1077 
1078 #define GEN6_CLIP_DW3_MIN_POINT_WIDTH__MASK			0x0ffe0000
1079 #define GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT			17
1080 #define GEN6_CLIP_DW3_MIN_POINT_WIDTH__RADIX			3
1081 #define GEN6_CLIP_DW3_MAX_POINT_WIDTH__MASK			0x0001ffc0
1082 #define GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT			6
1083 #define GEN6_CLIP_DW3_MAX_POINT_WIDTH__RADIX			3
1084 #define GEN6_CLIP_DW3_FORCE_RTAINDEX_ZERO			(0x1 << 5)
1085 #define GEN6_CLIP_DW3_MAX_VPINDEX__MASK				0x0000000f
1086 #define GEN6_CLIP_DW3_MAX_VPINDEX__SHIFT			0
1087 
1088 #define GEN6_3DSTATE_SF_DW1_DW3__SIZE				3
1089 
1090 #define GEN7_SF_DW1_DEPTH_FORMAT__MASK				0x00007000
1091 #define GEN7_SF_DW1_DEPTH_FORMAT__SHIFT				12
1092 #define GEN9_SF_DW1_LINE_WIDTH__MASK				0x3ffff000
1093 #define GEN9_SF_DW1_LINE_WIDTH__SHIFT				12
1094 #define GEN9_SF_DW1_LINE_WIDTH__RADIX				7
1095 #define GEN7_SF_DW1_LEGACY_DEPTH_OFFSET				(0x1 << 11)
1096 #define GEN7_SF_DW1_STATISTICS					(0x1 << 10)
1097 #define GEN7_SF_DW1_DEPTH_OFFSET_SOLID				(0x1 << 9)
1098 #define GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME			(0x1 << 8)
1099 #define GEN7_SF_DW1_DEPTH_OFFSET_POINT				(0x1 << 7)
1100 #define GEN7_SF_DW1_FILL_MODE_FRONT__MASK			0x00000060
1101 #define GEN7_SF_DW1_FILL_MODE_FRONT__SHIFT			5
1102 #define GEN7_SF_DW1_FILL_MODE_BACK__MASK			0x00000018
1103 #define GEN7_SF_DW1_FILL_MODE_BACK__SHIFT			3
1104 #define GEN7_SF_DW1_VIEWPORT_TRANSFORM				(0x1 << 1)
1105 #define GEN7_SF_DW1_FRONT_WINDING__MASK				0x00000001
1106 #define GEN7_SF_DW1_FRONT_WINDING__SHIFT			0
1107 
1108 #define GEN7_SF_DW2_AA_LINE_ENABLE				(0x1 << 31)
1109 #define GEN7_SF_DW2_CULL_MODE__MASK				0x60000000
1110 #define GEN7_SF_DW2_CULL_MODE__SHIFT				29
1111 #define GEN7_SF_DW2_LINE_WIDTH__MASK				0x0ffc0000
1112 #define GEN7_SF_DW2_LINE_WIDTH__SHIFT				18
1113 #define GEN7_SF_DW2_LINE_WIDTH__RADIX				7
1114 #define GEN7_SF_DW2_AA_LINE_CAP__MASK				0x00030000
1115 #define GEN7_SF_DW2_AA_LINE_CAP__SHIFT				16
1116 #define GEN7_SF_DW2_AA_LINE_CAP_0_5				(0x0 << 16)
1117 #define GEN7_SF_DW2_AA_LINE_CAP_1_0				(0x1 << 16)
1118 #define GEN7_SF_DW2_AA_LINE_CAP_2_0				(0x2 << 16)
1119 #define GEN7_SF_DW2_AA_LINE_CAP_4_0				(0x3 << 16)
1120 #define GEN75_SF_DW2_LINE_STIPPLE_ENABLE			(0x1 << 14)
1121 #define GEN7_SF_DW2_SCISSOR_ENABLE				(0x1 << 11)
1122 #define GEN7_SF_DW2_MSRASTMODE__MASK				0x00000300
1123 #define GEN7_SF_DW2_MSRASTMODE__SHIFT				8
1124 
1125 #define GEN7_SF_DW3_LINE_LAST_PIXEL_ENABLE			(0x1 << 31)
1126 #define GEN7_SF_DW3_TRI_PROVOKE__MASK				0x60000000
1127 #define GEN7_SF_DW3_TRI_PROVOKE__SHIFT				29
1128 #define GEN7_SF_DW3_LINE_PROVOKE__MASK				0x18000000
1129 #define GEN7_SF_DW3_LINE_PROVOKE__SHIFT				27
1130 #define GEN7_SF_DW3_TRIFAN_PROVOKE__MASK			0x06000000
1131 #define GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT			25
1132 #define GEN7_SF_DW3_TRUE_AA_LINE_DISTANCE			(0x1 << 14)
1133 #define GEN8_SF_DW3_SMOOTH_POINT_ENABLE				(0x1 << 13)
1134 #define GEN7_SF_DW3_SUBPIXEL__MASK				0x00001000
1135 #define GEN7_SF_DW3_SUBPIXEL__SHIFT				12
1136 #define GEN7_SF_DW3_SUBPIXEL_8BITS				(0x0 << 12)
1137 #define GEN7_SF_DW3_SUBPIXEL_4BITS				(0x1 << 12)
1138 #define GEN7_SF_DW3_USE_POINT_WIDTH				(0x1 << 11)
1139 #define GEN7_SF_DW3_POINT_WIDTH__MASK				0x000007ff
1140 #define GEN7_SF_DW3_POINT_WIDTH__SHIFT				0
1141 #define GEN7_SF_DW3_POINT_WIDTH__RADIX				3
1142 
1143 #define GEN7_3DSTATE_SBE_DW1__SIZE				13
1144 
1145 #define GEN8_SBE_DW1_FORCE_URB_READ_LEN				(0x1 << 29)
1146 #define GEN8_SBE_DW1_FORCE_URB_READ_OFFSET			(0x1 << 28)
1147 #define GEN7_SBE_DW1_ATTR_SWIZZLE__MASK				0x10000000
1148 #define GEN7_SBE_DW1_ATTR_SWIZZLE__SHIFT			28
1149 #define GEN7_SBE_DW1_ATTR_SWIZZLE_0_15				(0x0 << 28)
1150 #define GEN7_SBE_DW1_ATTR_SWIZZLE_16_31				(0x1 << 28)
1151 #define GEN7_SBE_DW1_ATTR_COUNT__MASK				0x0fc00000
1152 #define GEN7_SBE_DW1_ATTR_COUNT__SHIFT				22
1153 #define GEN7_SBE_DW1_ATTR_SWIZZLE_ENABLE			(0x1 << 21)
1154 #define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD__MASK		0x00100000
1155 #define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD__SHIFT		20
1156 #define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_UPPERLEFT		(0x0 << 20)
1157 #define GEN7_SBE_DW1_POINT_SPRITE_TEXCOORD_LOWERLEFT		(0x1 << 20)
1158 #define GEN8_SBE_DW1_PID_OVERRIDE_W				(0x1 << 19)
1159 #define GEN8_SBE_DW1_PID_OVERRIDE_Z				(0x1 << 18)
1160 #define GEN8_SBE_DW1_PID_OVERRIDE_Y				(0x1 << 17)
1161 #define GEN8_SBE_DW1_PID_OVERRIDE_X				(0x1 << 16)
1162 #define GEN7_SBE_DW1_URB_READ_LEN__MASK				0x0000f800
1163 #define GEN7_SBE_DW1_URB_READ_LEN__SHIFT			11
1164 #define GEN7_SBE_DW1_URB_READ_OFFSET__MASK			0x000003f0
1165 #define GEN7_SBE_DW1_URB_READ_OFFSET__SHIFT			4
1166 #define GEN8_SBE_DW1_URB_READ_OFFSET__MASK			0x000007e0
1167 #define GEN8_SBE_DW1_URB_READ_OFFSET__SHIFT			5
1168 #define GEN8_SBE_DW1_PID_OVERRIDE_ATTR__MASK			0x0000001f
1169 #define GEN8_SBE_DW1_PID_OVERRIDE_ATTR__SHIFT			0
1170 
1171 #define GEN8_3DSTATE_SBE_SWIZ_DW1_DW8__SIZE			8
1172 
1173 #define GEN8_SBE_SWIZ_HIGH__MASK				0xffff0000
1174 #define GEN8_SBE_SWIZ_HIGH__SHIFT				16
1175 #define GEN8_SBE_SWIZ_CONST_OVERRIDE_W				(0x1 << 15)
1176 #define GEN8_SBE_SWIZ_CONST_OVERRIDE_Z				(0x1 << 14)
1177 #define GEN8_SBE_SWIZ_CONST_OVERRIDE_Y				(0x1 << 13)
1178 #define GEN8_SBE_SWIZ_CONST_OVERRIDE_X				(0x1 << 12)
1179 #define GEN8_SBE_SWIZ_SWIZZLE_CONTROL				(0x1 << 11)
1180 #define GEN8_SBE_SWIZ_CONST__MASK				0x00000600
1181 #define GEN8_SBE_SWIZ_CONST__SHIFT				9
1182 #define GEN8_SBE_SWIZ_CONST_0000				(0x0 << 9)
1183 #define GEN8_SBE_SWIZ_CONST_0001_FLOAT				(0x1 << 9)
1184 #define GEN8_SBE_SWIZ_CONST_1111_FLOAT				(0x2 << 9)
1185 #define GEN8_SBE_SWIZ_CONST_PRIM_ID				(0x3 << 9)
1186 #define GEN8_SBE_SWIZ_SWIZZLE_SELECT__MASK			0x000000c0
1187 #define GEN8_SBE_SWIZ_SWIZZLE_SELECT__SHIFT			6
1188 #define GEN8_SBE_SWIZ_SRC_ATTR__MASK				0x0000001f
1189 #define GEN8_SBE_SWIZ_SRC_ATTR__SHIFT				0
1190 
1191 #define GEN6_3DSTATE_SF__SIZE					20
1192 
1193 
1194 
1195 
1196 
1197 
1198 
1199 
1200 
1201 
1202 
1203 
1204 
1205 
1206 
1207 
1208 
1209 
1210 
1211 
1212 #define GEN7_3DSTATE_SBE__SIZE					14
1213 
1214 
1215 
1216 
1217 
1218 
1219 
1220 
1221 
1222 
1223 
1224 
1225 #define GEN9_SBE_DW_ACTIVE_COMPONENT__MASK			0x00000003
1226 #define GEN9_SBE_DW_ACTIVE_COMPONENT__SHIFT			0
1227 #define GEN9_SBE_DW_ACTIVE_COMPONENT_NONE			0x0
1228 #define GEN9_SBE_DW_ACTIVE_COMPONENT_XY				0x1
1229 #define GEN9_SBE_DW_ACTIVE_COMPONENT_XYZ			0x2
1230 #define GEN9_SBE_DW_ACTIVE_COMPONENT_XYZW			0x3
1231 
1232 #define GEN8_3DSTATE_SBE_SWIZ__SIZE				11
1233 
1234 
1235 
1236 
1237 #define GEN8_3DSTATE_RASTER__SIZE				5
1238 
1239 
1240 #define GEN9_RASTER_DW1_Z_TEST_FAR_ENABLE			(0x1 << 26)
1241 #define GEN8_RASTER_DW1_API__MASK				0x00c00000
1242 #define GEN8_RASTER_DW1_API__SHIFT				22
1243 #define GEN8_RASTER_DW1_API_DX9_OGL				(0x0 << 22)
1244 #define GEN8_RASTER_DW1_API_DX10				(0x1 << 22)
1245 #define GEN8_RASTER_DW1_API_DX10_1				(0x2 << 22)
1246 #define GEN8_RASTER_DW1_FRONT_WINDING__MASK			0x00200000
1247 #define GEN8_RASTER_DW1_FRONT_WINDING__SHIFT			21
1248 #define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT__MASK		0x001c0000
1249 #define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT__SHIFT		18
1250 #define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_0	(0x0 << 18)
1251 #define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_1	(0x1 << 18)
1252 #define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_2	(0x2 << 18)
1253 #define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_4	(0x3 << 18)
1254 #define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_8	(0x4 << 18)
1255 #define GEN8_RASTER_DW1_FORCED_SAMPLE_COUNT_NUMRASTSAMPLES_16	(0x5 << 18)
1256 #define GEN8_RASTER_DW1_CULL_MODE__MASK				0x00030000
1257 #define GEN8_RASTER_DW1_CULL_MODE__SHIFT			16
1258 #define GEN8_RASTER_DW1_FORCE_MULTISAMPLE_ENABLE		(0x1 << 14)
1259 #define GEN8_RASTER_DW1_SMOOTH_POINT_ENABLE			(0x1 << 13)
1260 #define GEN8_RASTER_DW1_DX_MULTISAMPLE_ENABLE			(0x1 << 12)
1261 #define GEN8_RASTER_DW1_DX_MSRASTMODE__MASK			0x00000c00
1262 #define GEN8_RASTER_DW1_DX_MSRASTMODE__SHIFT			10
1263 #define GEN8_RASTER_DW1_DEPTH_OFFSET_SOLID			(0x1 << 9)
1264 #define GEN8_RASTER_DW1_DEPTH_OFFSET_WIREFRAME			(0x1 << 8)
1265 #define GEN8_RASTER_DW1_DEPTH_OFFSET_POINT			(0x1 << 7)
1266 #define GEN8_RASTER_DW1_FILL_MODE_FRONT__MASK			0x00000060
1267 #define GEN8_RASTER_DW1_FILL_MODE_FRONT__SHIFT			5
1268 #define GEN8_RASTER_DW1_FILL_MODE_BACK__MASK			0x00000018
1269 #define GEN8_RASTER_DW1_FILL_MODE_BACK__SHIFT			3
1270 #define GEN8_RASTER_DW1_AA_LINE_ENABLE				(0x1 << 2)
1271 #define GEN8_RASTER_DW1_SCISSOR_ENABLE				(0x1 << 1)
1272 #define GEN8_RASTER_DW1_Z_TEST_ENABLE				(0x1 << 0)
1273 #define GEN9_RASTER_DW1_Z_TEST_NEAR_ENABLE			(0x1 << 0)
1274 
1275 
1276 
1277 
1278 #define GEN6_3DSTATE_WM__SIZE					9
1279 
1280 
1281 #define GEN6_WM_DW1_KERNEL0_ADDR__MASK				0xffffffc0
1282 #define GEN6_WM_DW1_KERNEL0_ADDR__SHIFT				6
1283 #define GEN6_WM_DW1_KERNEL0_ADDR__SHR				6
1284 
1285 
1286 
1287 #define GEN6_WM_DW4_STATISTICS					(0x1 << 31)
1288 #define GEN6_WM_DW4_DEPTH_CLEAR					(0x1 << 30)
1289 #define GEN6_WM_DW4_DEPTH_RESOLVE				(0x1 << 28)
1290 #define GEN6_WM_DW4_HIZ_RESOLVE					(0x1 << 27)
1291 #define GEN6_WM_DW4_URB_GRF_START0__MASK			0x007f0000
1292 #define GEN6_WM_DW4_URB_GRF_START0__SHIFT			16
1293 #define GEN6_WM_DW4_URB_GRF_START1__MASK			0x00007f00
1294 #define GEN6_WM_DW4_URB_GRF_START1__SHIFT			8
1295 #define GEN6_WM_DW4_URB_GRF_START2__MASK			0x0000007f
1296 #define GEN6_WM_DW4_URB_GRF_START2__SHIFT			0
1297 
1298 #define GEN6_WM_DW5_MAX_THREADS__MASK				0xfe000000
1299 #define GEN6_WM_DW5_MAX_THREADS__SHIFT				25
1300 #define GEN6_WM_DW5_LEGACY_LINE_RAST				(0x1 << 23)
1301 #define GEN6_WM_DW5_PS_KILL_PIXEL				(0x1 << 22)
1302 #define GEN6_WM_DW5_PS_COMPUTE_DEPTH				(0x1 << 21)
1303 #define GEN6_WM_DW5_PS_USE_DEPTH				(0x1 << 20)
1304 #define GEN6_WM_DW5_PS_DISPATCH_ENABLE				(0x1 << 19)
1305 #define GEN6_WM_DW5_AA_LINE_CAP__MASK				0x00030000
1306 #define GEN6_WM_DW5_AA_LINE_CAP__SHIFT				16
1307 #define GEN6_WM_DW5_AA_LINE_CAP_0_5				(0x0 << 16)
1308 #define GEN6_WM_DW5_AA_LINE_CAP_1_0				(0x1 << 16)
1309 #define GEN6_WM_DW5_AA_LINE_CAP_2_0				(0x2 << 16)
1310 #define GEN6_WM_DW5_AA_LINE_CAP_4_0				(0x3 << 16)
1311 #define GEN6_WM_DW5_AA_LINE_WIDTH__MASK				0x0000c000
1312 #define GEN6_WM_DW5_AA_LINE_WIDTH__SHIFT			14
1313 #define GEN6_WM_DW5_AA_LINE_WIDTH_0_5				(0x0 << 14)
1314 #define GEN6_WM_DW5_AA_LINE_WIDTH_1_0				(0x1 << 14)
1315 #define GEN6_WM_DW5_AA_LINE_WIDTH_2_0				(0x2 << 14)
1316 #define GEN6_WM_DW5_AA_LINE_WIDTH_4_0				(0x3 << 14)
1317 #define GEN6_WM_DW5_POLY_STIPPLE_ENABLE				(0x1 << 13)
1318 #define GEN6_WM_DW5_LINE_STIPPLE_ENABLE				(0x1 << 11)
1319 #define GEN6_WM_DW5_PS_COMPUTE_OMASK				(0x1 << 9)
1320 #define GEN6_WM_DW5_PS_USE_W					(0x1 << 8)
1321 #define GEN6_WM_DW5_PS_DUAL_SOURCE_BLEND			(0x1 << 7)
1322 #define GEN6_WM_DW5_PS_DISPATCH_MODE__MASK			0x00000007
1323 #define GEN6_WM_DW5_PS_DISPATCH_MODE__SHIFT			0
1324 
1325 #define GEN6_WM_DW6_SF_ATTR_COUNT__MASK				0x03f00000
1326 #define GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT			20
1327 #define GEN6_WM_DW6_PS_POSOFFSET__MASK				0x000c0000
1328 #define GEN6_WM_DW6_PS_POSOFFSET__SHIFT				18
1329 #define GEN6_WM_DW6_ZW_INTERP__MASK				0x00030000
1330 #define GEN6_WM_DW6_ZW_INTERP__SHIFT				16
1331 #define GEN6_WM_DW6_BARYCENTRIC_INTERP__MASK			0x0000fc00
1332 #define GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT			10
1333 #define GEN6_WM_DW6_POINT_RASTRULE__MASK			0x00000200
1334 #define GEN6_WM_DW6_POINT_RASTRULE__SHIFT			9
1335 #define GEN6_WM_DW6_POINT_RASTRULE_UPPER_LEFT			(0x0 << 9)
1336 #define GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT			(0x1 << 9)
1337 #define GEN6_WM_DW6_MSRASTMODE__MASK				0x00000006
1338 #define GEN6_WM_DW6_MSRASTMODE__SHIFT				1
1339 #define GEN6_WM_DW6_MSDISPMODE__MASK				0x00000001
1340 #define GEN6_WM_DW6_MSDISPMODE__SHIFT				0
1341 #define GEN6_WM_DW6_MSDISPMODE_PERSAMPLE			0x0
1342 #define GEN6_WM_DW6_MSDISPMODE_PERPIXEL				0x1
1343 
1344 #define GEN6_WM_DW7_KERNEL1_ADDR__MASK				0xffffffc0
1345 #define GEN6_WM_DW7_KERNEL1_ADDR__SHIFT				6
1346 #define GEN6_WM_DW7_KERNEL1_ADDR__SHR				6
1347 
1348 #define GEN6_WM_DW8_KERNEL2_ADDR__MASK				0xffffffc0
1349 #define GEN6_WM_DW8_KERNEL2_ADDR__SHIFT				6
1350 #define GEN6_WM_DW8_KERNEL2_ADDR__SHR				6
1351 
1352 
1353 #define GEN7_WM_DW1_STATISTICS					(0x1 << 31)
1354 #define GEN7_WM_DW1_LEGACY_DEPTH_CLEAR				(0x1 << 30)
1355 #define GEN7_WM_DW1_PS_DISPATCH_ENABLE				(0x1 << 29)
1356 #define GEN7_WM_DW1_LEGACY_DEPTH_RESOLVE			(0x1 << 28)
1357 #define GEN7_WM_DW1_LEGACY_HIZ_RESOLVE				(0x1 << 27)
1358 #define GEN7_WM_DW1_LEGACY_LINE_RAST				(0x1 << 26)
1359 #define GEN7_WM_DW1_PS_KILL_PIXEL				(0x1 << 25)
1360 #define GEN7_WM_DW1_PSCDEPTH__MASK				0x01800000
1361 #define GEN7_WM_DW1_PSCDEPTH__SHIFT				23
1362 #define GEN7_WM_DW1_EDSC__MASK					0x00600000
1363 #define GEN7_WM_DW1_EDSC__SHIFT					21
1364 #define GEN7_WM_DW1_PS_USE_DEPTH				(0x1 << 20)
1365 #define GEN7_WM_DW1_PS_USE_W					(0x1 << 19)
1366 #define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE__MASK			0x00180000
1367 #define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE__SHIFT		19
1368 #define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_NORMAL		(0x0 << 19)
1369 #define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_OFF			(0x1 << 19)
1370 #define GEN8_WM_DW1_FORCE_DISPATCH_ENABLE_ON			(0x2 << 19)
1371 #define GEN7_WM_DW1_ZW_INTERP__MASK				0x00060000
1372 #define GEN7_WM_DW1_ZW_INTERP__SHIFT				17
1373 #define GEN7_WM_DW1_BARYCENTRIC_INTERP__MASK			0x0001f800
1374 #define GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT			11
1375 #define GEN7_WM_DW1_PS_USE_COVERAGE_MASK			(0x1 << 10)
1376 #define GEN7_WM_DW1_AA_LINE_CAP__MASK				0x00000300
1377 #define GEN7_WM_DW1_AA_LINE_CAP__SHIFT				8
1378 #define GEN7_WM_DW1_AA_LINE_CAP_0_5				(0x0 << 8)
1379 #define GEN7_WM_DW1_AA_LINE_CAP_1_0				(0x1 << 8)
1380 #define GEN7_WM_DW1_AA_LINE_CAP_2_0				(0x2 << 8)
1381 #define GEN7_WM_DW1_AA_LINE_CAP_4_0				(0x3 << 8)
1382 #define GEN7_WM_DW1_AA_LINE_WIDTH__MASK				0x000000c0
1383 #define GEN7_WM_DW1_AA_LINE_WIDTH__SHIFT			6
1384 #define GEN7_WM_DW1_AA_LINE_WIDTH_0_5				(0x0 << 6)
1385 #define GEN7_WM_DW1_AA_LINE_WIDTH_1_0				(0x1 << 6)
1386 #define GEN7_WM_DW1_AA_LINE_WIDTH_2_0				(0x2 << 6)
1387 #define GEN7_WM_DW1_AA_LINE_WIDTH_4_0				(0x3 << 6)
1388 #define GEN75_WM_DW1_RT_INDEPENDENT_RAST			(0x1 << 5)
1389 #define GEN7_WM_DW1_POLY_STIPPLE_ENABLE				(0x1 << 4)
1390 #define GEN7_WM_DW1_LINE_STIPPLE_ENABLE				(0x1 << 3)
1391 #define GEN7_WM_DW1_POINT_RASTRULE__MASK			0x00000004
1392 #define GEN7_WM_DW1_POINT_RASTRULE__SHIFT			2
1393 #define GEN7_WM_DW1_POINT_RASTRULE_UPPER_LEFT			(0x0 << 2)
1394 #define GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT			(0x1 << 2)
1395 #define GEN7_WM_DW1_MSRASTMODE__MASK				0x00000003
1396 #define GEN7_WM_DW1_MSRASTMODE__SHIFT				0
1397 #define GEN8_WM_DW1_FORCE_KILL_PIXEL__MASK			0x00000003
1398 #define GEN8_WM_DW1_FORCE_KILL_PIXEL__SHIFT			0
1399 #define GEN8_WM_DW1_FORCE_KILL_PIXEL_NORMAL			0x0
1400 #define GEN8_WM_DW1_FORCE_KILL_PIXEL_OFF			0x1
1401 #define GEN8_WM_DW1_FORCE_KILL_PIXEL_ON				0x2
1402 
1403 #define GEN7_WM_DW2_MSDISPMODE__MASK				0x80000000
1404 #define GEN7_WM_DW2_MSDISPMODE__SHIFT				31
1405 #define GEN7_WM_DW2_MSDISPMODE_PERSAMPLE			(0x0 << 31)
1406 #define GEN7_WM_DW2_MSDISPMODE_PERPIXEL				(0x1 << 31)
1407 #define GEN75_WM_DW2_PS_UAV_ONLY				(0x1 << 30)
1408 
1409 #define GEN8_3DSTATE_WM_CHROMAKEY__SIZE				2
1410 
1411 
1412 #define GEN8_CHROMAKEY_DW1_KILL_ENABLE				(0x1 << 31)
1413 
1414 #define GEN8_3DSTATE_WM_DEPTH_STENCIL__SIZE			4
1415 
1416 
1417 #define GEN8_ZS_DW1_STENCIL_FAIL_OP__MASK			0xe0000000
1418 #define GEN8_ZS_DW1_STENCIL_FAIL_OP__SHIFT			29
1419 #define GEN8_ZS_DW1_STENCIL_ZFAIL_OP__MASK			0x1c000000
1420 #define GEN8_ZS_DW1_STENCIL_ZFAIL_OP__SHIFT			26
1421 #define GEN8_ZS_DW1_STENCIL_ZPASS_OP__MASK			0x03800000
1422 #define GEN8_ZS_DW1_STENCIL_ZPASS_OP__SHIFT			23
1423 #define GEN8_ZS_DW1_STENCIL1_FUNC__MASK				0x00700000
1424 #define GEN8_ZS_DW1_STENCIL1_FUNC__SHIFT			20
1425 #define GEN8_ZS_DW1_STENCIL1_FAIL_OP__MASK			0x000e0000
1426 #define GEN8_ZS_DW1_STENCIL1_FAIL_OP__SHIFT			17
1427 #define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__MASK			0x0001c000
1428 #define GEN8_ZS_DW1_STENCIL1_ZFAIL_OP__SHIFT			14
1429 #define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__MASK			0x00003800
1430 #define GEN8_ZS_DW1_STENCIL1_ZPASS_OP__SHIFT			11
1431 #define GEN8_ZS_DW1_STENCIL_FUNC__MASK				0x00000700
1432 #define GEN8_ZS_DW1_STENCIL_FUNC__SHIFT				8
1433 #define GEN8_ZS_DW1_DEPTH_FUNC__MASK				0x000000e0
1434 #define GEN8_ZS_DW1_DEPTH_FUNC__SHIFT				5
1435 #define GEN8_ZS_DW1_STENCIL1_ENABLE				(0x1 << 4)
1436 #define GEN8_ZS_DW1_STENCIL_TEST_ENABLE				(0x1 << 3)
1437 #define GEN8_ZS_DW1_STENCIL_WRITE_ENABLE			(0x1 << 2)
1438 #define GEN8_ZS_DW1_DEPTH_TEST_ENABLE				(0x1 << 1)
1439 #define GEN8_ZS_DW1_DEPTH_WRITE_ENABLE				(0x1 << 0)
1440 
1441 #define GEN8_ZS_DW2_STENCIL_TEST_MASK__MASK			0xff000000
1442 #define GEN8_ZS_DW2_STENCIL_TEST_MASK__SHIFT			24
1443 #define GEN8_ZS_DW2_STENCIL_WRITE_MASK__MASK			0x00ff0000
1444 #define GEN8_ZS_DW2_STENCIL_WRITE_MASK__SHIFT			16
1445 #define GEN8_ZS_DW2_STENCIL1_TEST_MASK__MASK			0x0000ff00
1446 #define GEN8_ZS_DW2_STENCIL1_TEST_MASK__SHIFT			8
1447 #define GEN8_ZS_DW2_STENCIL1_WRITE_MASK__MASK			0x000000ff
1448 #define GEN8_ZS_DW2_STENCIL1_WRITE_MASK__SHIFT			0
1449 
1450 #define GEN9_ZS_DW3_STENCIL_REF__MASK				0x0000ff00
1451 #define GEN9_ZS_DW3_STENCIL_REF__SHIFT				8
1452 #define GEN9_ZS_DW3_STENCIL1_REF__MASK				0x000000ff
1453 #define GEN9_ZS_DW3_STENCIL1_REF__SHIFT				0
1454 
1455 #define GEN8_3DSTATE_WM_HZ_OP__SIZE				5
1456 
1457 
1458 #define GEN8_WM_HZ_DW1_STENCIL_CLEAR				(0x1 << 31)
1459 #define GEN8_WM_HZ_DW1_DEPTH_CLEAR				(0x1 << 30)
1460 #define GEN8_WM_HZ_DW1_SCISSOR_ENABLE				(0x1 << 29)
1461 #define GEN8_WM_HZ_DW1_DEPTH_RESOLVE				(0x1 << 28)
1462 #define GEN8_WM_HZ_DW1_HIZ_RESOLVE				(0x1 << 27)
1463 #define GEN8_WM_HZ_DW1_PIXEL_OFFSET_ENABLE			(0x1 << 26)
1464 #define GEN8_WM_HZ_DW1_FULL_SURFACE_DEPTH_CLEAR			(0x1 << 25)
1465 #define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__MASK		0x00ff0000
1466 #define GEN8_WM_HZ_DW1_STENCIL_CLEAR_VALUE__SHIFT		16
1467 #define GEN8_WM_HZ_DW1_NUM_SAMPLES__MASK			0x0000e000
1468 #define GEN8_WM_HZ_DW1_NUM_SAMPLES__SHIFT			13
1469 
1470 #define GEN8_WM_HZ_DW2_RECT_MIN_Y__MASK				0xffff0000
1471 #define GEN8_WM_HZ_DW2_RECT_MIN_Y__SHIFT			16
1472 #define GEN8_WM_HZ_DW2_RECT_MIN_X__MASK				0x0000ffff
1473 #define GEN8_WM_HZ_DW2_RECT_MIN_X__SHIFT			0
1474 
1475 #define GEN8_WM_HZ_DW3_RECT_MAX_Y__MASK				0xffff0000
1476 #define GEN8_WM_HZ_DW3_RECT_MAX_Y__SHIFT			16
1477 #define GEN8_WM_HZ_DW3_RECT_MAX_X__MASK				0x0000ffff
1478 #define GEN8_WM_HZ_DW3_RECT_MAX_X__SHIFT			0
1479 
1480 #define GEN8_WM_HZ_DW4_SAMPLE_MASK__MASK			0x0000ffff
1481 #define GEN8_WM_HZ_DW4_SAMPLE_MASK__SHIFT			0
1482 
1483 #define GEN7_3DSTATE_PS__SIZE					12
1484 
1485 
1486 #define GEN7_PS_DW1_KERNEL0_ADDR__MASK				0xffffffc0
1487 #define GEN7_PS_DW1_KERNEL0_ADDR__SHIFT				6
1488 #define GEN7_PS_DW1_KERNEL0_ADDR__SHR				6
1489 
1490 
1491 
1492 #define GEN7_PS_DW4_MAX_THREADS__MASK				0xff000000
1493 #define GEN7_PS_DW4_MAX_THREADS__SHIFT				24
1494 #define GEN75_PS_DW4_MAX_THREADS__MASK				0xff800000
1495 #define GEN75_PS_DW4_MAX_THREADS__SHIFT				23
1496 #define GEN75_PS_DW4_SAMPLE_MASK__MASK				0x000ff000
1497 #define GEN75_PS_DW4_SAMPLE_MASK__SHIFT				12
1498 #define GEN7_PS_DW4_PUSH_CONSTANT_ENABLE			(0x1 << 11)
1499 #define GEN7_PS_DW4_ATTR_ENABLE					(0x1 << 10)
1500 #define GEN7_PS_DW4_COMPUTE_OMASK				(0x1 << 9)
1501 #define GEN7_PS_DW4_RT_FAST_CLEAR				(0x1 << 8)
1502 #define GEN7_PS_DW4_DUAL_SOURCE_BLEND				(0x1 << 7)
1503 #define GEN7_PS_DW4_RT_RESOLVE					(0x1 << 6)
1504 #define GEN75_PS_DW4_ACCESS_UAV					(0x1 << 5)
1505 #define GEN7_PS_DW4_POSOFFSET__MASK				0x00000018
1506 #define GEN7_PS_DW4_POSOFFSET__SHIFT				3
1507 #define GEN7_PS_DW4_DISPATCH_MODE__MASK				0x00000007
1508 #define GEN7_PS_DW4_DISPATCH_MODE__SHIFT			0
1509 
1510 #define GEN7_PS_DW5_URB_GRF_START0__MASK			0x007f0000
1511 #define GEN7_PS_DW5_URB_GRF_START0__SHIFT			16
1512 #define GEN7_PS_DW5_URB_GRF_START1__MASK			0x00007f00
1513 #define GEN7_PS_DW5_URB_GRF_START1__SHIFT			8
1514 #define GEN7_PS_DW5_URB_GRF_START2__MASK			0x0000007f
1515 #define GEN7_PS_DW5_URB_GRF_START2__SHIFT			0
1516 
1517 #define GEN7_PS_DW6_KERNEL1_ADDR__MASK				0xffffffc0
1518 #define GEN7_PS_DW6_KERNEL1_ADDR__SHIFT				6
1519 #define GEN7_PS_DW6_KERNEL1_ADDR__SHR				6
1520 
1521 #define GEN7_PS_DW7_KERNEL2_ADDR__MASK				0xffffffc0
1522 #define GEN7_PS_DW7_KERNEL2_ADDR__SHIFT				6
1523 #define GEN7_PS_DW7_KERNEL2_ADDR__SHR				6
1524 
1525 
1526 
1527 #define GEN8_PS_DW1_KERNEL0_ADDR__MASK				0xffffffc0
1528 #define GEN8_PS_DW1_KERNEL0_ADDR__SHIFT				6
1529 #define GEN8_PS_DW1_KERNEL0_ADDR__SHR				6
1530 
1531 
1532 
1533 
1534 
1535 #define GEN8_PS_DW6_MAX_THREADS__MASK				0xff800000
1536 #define GEN8_PS_DW6_MAX_THREADS__SHIFT				23
1537 #define GEN8_PS_DW6_PUSH_CONSTANT_ENABLE			(0x1 << 11)
1538 #define GEN8_PS_DW6_RT_FAST_CLEAR				(0x1 << 8)
1539 #define GEN8_PS_DW6_RT_RESOLVE					(0x1 << 6)
1540 #define GEN8_PS_DW6_POSOFFSET__MASK				0x00000018
1541 #define GEN8_PS_DW6_POSOFFSET__SHIFT				3
1542 #define GEN8_PS_DW6_DISPATCH_MODE__MASK				0x00000007
1543 #define GEN8_PS_DW6_DISPATCH_MODE__SHIFT			0
1544 
1545 #define GEN8_PS_DW7_URB_GRF_START0__MASK			0x007f0000
1546 #define GEN8_PS_DW7_URB_GRF_START0__SHIFT			16
1547 #define GEN8_PS_DW7_URB_GRF_START1__MASK			0x00007f00
1548 #define GEN8_PS_DW7_URB_GRF_START1__SHIFT			8
1549 #define GEN8_PS_DW7_URB_GRF_START2__MASK			0x0000007f
1550 #define GEN8_PS_DW7_URB_GRF_START2__SHIFT			0
1551 
1552 #define GEN8_PS_DW8_KERNEL1_ADDR__MASK				0xffffffc0
1553 #define GEN8_PS_DW8_KERNEL1_ADDR__SHIFT				6
1554 #define GEN8_PS_DW8_KERNEL1_ADDR__SHR				6
1555 
1556 
1557 #define GEN8_PS_DW10_KERNEL2_ADDR__MASK				0xffffffc0
1558 #define GEN8_PS_DW10_KERNEL2_ADDR__SHIFT			6
1559 #define GEN8_PS_DW10_KERNEL2_ADDR__SHR				6
1560 
1561 
1562 #define GEN8_3DSTATE_PS_EXTRA__SIZE				2
1563 
1564 
1565 #define GEN8_PSX_DW1_VALID					(0x1 << 31)
1566 #define GEN8_PSX_DW1_UAV_ONLY					(0x1 << 30)
1567 #define GEN8_PSX_DW1_COMPUTE_OMASK				(0x1 << 29)
1568 #define GEN8_PSX_DW1_KILL_PIXEL					(0x1 << 28)
1569 #define GEN8_PSX_DW1_PSCDEPTH__MASK				0x0c000000
1570 #define GEN8_PSX_DW1_PSCDEPTH__SHIFT				26
1571 #define GEN8_PSX_DW1_FORCE_COMPUTE_DEPTH			(0x1 << 25)
1572 #define GEN8_PSX_DW1_USE_DEPTH					(0x1 << 24)
1573 #define GEN8_PSX_DW1_USE_W					(0x1 << 23)
1574 #define GEN8_PSX_DW1_ATTR_ENABLE				(0x1 << 8)
1575 #define GEN8_PSX_DW1_DISABLE_ALPHA_TO_COVERAGE			(0x1 << 7)
1576 #define GEN8_PSX_DW1_PER_SAMPLE					(0x1 << 6)
1577 #define GEN8_PSX_DW1_COMPUTE_STENCIL				(0x1 << 5)
1578 #define GEN8_PSX_DW1_ACCESS_UAV					(0x1 << 2)
1579 #define GEN8_PSX_DW1_USE_COVERAGE_MASK				(0x1 << 1)
1580 
1581 #define GEN8_3DSTATE_PS_BLEND__SIZE				2
1582 
1583 
1584 #define GEN8_PS_BLEND_DW1_ALPHA_TO_COVERAGE			(0x1 << 31)
1585 #define GEN8_PS_BLEND_DW1_WRITABLE_RT				(0x1 << 30)
1586 #define GEN8_PS_BLEND_DW1_RT0_BLEND_ENABLE			(0x1 << 29)
1587 #define GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__MASK		0x1f000000
1588 #define GEN8_PS_BLEND_DW1_RT0_SRC_ALPHA_FACTOR__SHIFT		24
1589 #define GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__MASK		0x00f80000
1590 #define GEN8_PS_BLEND_DW1_RT0_DST_ALPHA_FACTOR__SHIFT		19
1591 #define GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__MASK		0x0007c000
1592 #define GEN8_PS_BLEND_DW1_RT0_SRC_COLOR_FACTOR__SHIFT		14
1593 #define GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__MASK		0x00003e00
1594 #define GEN8_PS_BLEND_DW1_RT0_DST_COLOR_FACTOR__SHIFT		9
1595 #define GEN8_PS_BLEND_DW1_ALPHA_TEST_ENABLE			(0x1 << 8)
1596 #define GEN8_PS_BLEND_DW1_RT0_INDEPENDENT_ALPHA_ENABLE		(0x1 << 7)
1597 
1598 #define GEN6_3DSTATE_CONSTANT_ANY__SIZE				11
1599 
1600 #define GEN6_CONSTANT_DW0_BUFFER_ENABLES__MASK			0x0000f000
1601 #define GEN6_CONSTANT_DW0_BUFFER_ENABLES__SHIFT			12
1602 #define GEN6_CONSTANT_DW0_MOCS__MASK				0x00000f00
1603 #define GEN6_CONSTANT_DW0_MOCS__SHIFT				8
1604 
1605 #define GEN6_CONSTANT_DW_ADDR_READ_LEN__MASK			0x0000001f
1606 #define GEN6_CONSTANT_DW_ADDR_READ_LEN__SHIFT			0
1607 #define GEN6_CONSTANT_DW_ADDR_ADDR__MASK			0xffffffe0
1608 #define GEN6_CONSTANT_DW_ADDR_ADDR__SHIFT			5
1609 #define GEN6_CONSTANT_DW_ADDR_ADDR__SHR				5
1610 
1611 
1612 #define GEN8_CONSTANT_DW0_MOCS__MASK				0x00007f00
1613 #define GEN8_CONSTANT_DW0_MOCS__SHIFT				8
1614 
1615 #define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__MASK		0xffff0000
1616 #define GEN7_CONSTANT_DW1_BUFFER1_READ_LEN__SHIFT		16
1617 #define GEN7_CONSTANT_DW1_BUFFER0_READ_LEN__MASK		0x0000ffff
1618 #define GEN7_CONSTANT_DW1_BUFFER0_READ_LEN__SHIFT		0
1619 
1620 #define GEN7_CONSTANT_DW2_BUFFER3_READ_LEN__MASK		0xffff0000
1621 #define GEN7_CONSTANT_DW2_BUFFER3_READ_LEN__SHIFT		16
1622 #define GEN7_CONSTANT_DW2_BUFFER2_READ_LEN__MASK		0x0000ffff
1623 #define GEN7_CONSTANT_DW2_BUFFER2_READ_LEN__SHIFT		0
1624 
1625 #define GEN7_CONSTANT_DW_ADDR_MOCS__MASK			0x0000001f
1626 #define GEN7_CONSTANT_DW_ADDR_MOCS__SHIFT			0
1627 #define GEN7_CONSTANT_DW_ADDR_ADDR__MASK			0xffffffe0
1628 #define GEN7_CONSTANT_DW_ADDR_ADDR__SHIFT			5
1629 #define GEN7_CONSTANT_DW_ADDR_ADDR__SHR				5
1630 
1631 #define GEN8_CONSTANT_DW_ADDR_ADDR__MASK			0xffffffe0
1632 #define GEN8_CONSTANT_DW_ADDR_ADDR__SHIFT			5
1633 #define GEN8_CONSTANT_DW_ADDR_ADDR__SHR				5
1634 
1635 #define GEN6_3DSTATE_SAMPLE_MASK__SIZE				2
1636 
1637 
1638 #define GEN6_SAMPLE_MASK_DW1_VAL__MASK				0x0000000f
1639 #define GEN6_SAMPLE_MASK_DW1_VAL__SHIFT				0
1640 #define GEN7_SAMPLE_MASK_DW1_VAL__MASK				0x000000ff
1641 #define GEN7_SAMPLE_MASK_DW1_VAL__SHIFT				0
1642 #define GEN8_SAMPLE_MASK_DW1_VAL__MASK				0x0000ffff
1643 #define GEN8_SAMPLE_MASK_DW1_VAL__SHIFT				0
1644 
1645 #define GEN6_3DSTATE_DRAWING_RECTANGLE__SIZE			4
1646 
1647 #define GEN8_DRAWING_RECTANGLE_DW0_CORE_MODE_SELECT__MASK	0x0000c000
1648 #define GEN8_DRAWING_RECTANGLE_DW0_CORE_MODE_SELECT__SHIFT	14
1649 
1650 #define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__MASK			0xffff0000
1651 #define GEN6_DRAWING_RECTANGLE_DW1_MIN_Y__SHIFT			16
1652 #define GEN6_DRAWING_RECTANGLE_DW1_MIN_X__MASK			0x0000ffff
1653 #define GEN6_DRAWING_RECTANGLE_DW1_MIN_X__SHIFT			0
1654 
1655 #define GEN6_DRAWING_RECTANGLE_DW2_MAX_Y__MASK			0xffff0000
1656 #define GEN6_DRAWING_RECTANGLE_DW2_MAX_Y__SHIFT			16
1657 #define GEN6_DRAWING_RECTANGLE_DW2_MAX_X__MASK			0x0000ffff
1658 #define GEN6_DRAWING_RECTANGLE_DW2_MAX_X__SHIFT			0
1659 
1660 #define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_Y__MASK		0xffff0000
1661 #define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_Y__SHIFT		16
1662 #define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__MASK		0x0000ffff
1663 #define GEN6_DRAWING_RECTANGLE_DW3_ORIGIN_X__SHIFT		0
1664 
1665 #define GEN6_3DSTATE_DEPTH_BUFFER__SIZE				8
1666 
1667 
1668 #define GEN6_DEPTH_DW1_TYPE__MASK				0xe0000000
1669 #define GEN6_DEPTH_DW1_TYPE__SHIFT				29
1670 #define GEN6_DEPTH_DW1_TILING__MASK				0x0c000000
1671 #define GEN6_DEPTH_DW1_TILING__SHIFT				26
1672 #define GEN6_DEPTH_DW1_STR_MODE__MASK				0x01800000
1673 #define GEN6_DEPTH_DW1_STR_MODE__SHIFT				23
1674 #define GEN6_DEPTH_DW1_HIZ_ENABLE				(0x1 << 22)
1675 #define GEN6_DEPTH_DW1_SEPARATE_STENCIL				(0x1 << 21)
1676 #define GEN6_DEPTH_DW1_FORMAT__MASK				0x001c0000
1677 #define GEN6_DEPTH_DW1_FORMAT__SHIFT				18
1678 #define GEN6_DEPTH_DW1_PITCH__MASK				0x0001ffff
1679 #define GEN6_DEPTH_DW1_PITCH__SHIFT				0
1680 
1681 
1682 #define GEN6_DEPTH_DW3_HEIGHT__MASK				0xfff80000
1683 #define GEN6_DEPTH_DW3_HEIGHT__SHIFT				19
1684 #define GEN6_DEPTH_DW3_WIDTH__MASK				0x0007ffc0
1685 #define GEN6_DEPTH_DW3_WIDTH__SHIFT				6
1686 #define GEN6_DEPTH_DW3_LOD__MASK				0x0000003c
1687 #define GEN6_DEPTH_DW3_LOD__SHIFT				2
1688 #define GEN6_DEPTH_DW3_MIPLAYOUT__MASK				0x00000002
1689 #define GEN6_DEPTH_DW3_MIPLAYOUT__SHIFT				1
1690 #define GEN6_DEPTH_DW3_MIPLAYOUT_BELOW				(0x0 << 1)
1691 #define GEN6_DEPTH_DW3_MIPLAYOUT_RIGHT				(0x1 << 1)
1692 
1693 #define GEN6_DEPTH_DW4_DEPTH__MASK				0xffe00000
1694 #define GEN6_DEPTH_DW4_DEPTH__SHIFT				21
1695 #define GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__MASK			0x001ffc00
1696 #define GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT			10
1697 #define GEN6_DEPTH_DW4_RT_VIEW_EXTENT__MASK			0x000003fe
1698 #define GEN6_DEPTH_DW4_RT_VIEW_EXTENT__SHIFT			1
1699 
1700 #define GEN6_DEPTH_DW5_OFFSET_Y__MASK				0xffff0000
1701 #define GEN6_DEPTH_DW5_OFFSET_Y__SHIFT				16
1702 #define GEN6_DEPTH_DW5_OFFSET_X__MASK				0x0000ffff
1703 #define GEN6_DEPTH_DW5_OFFSET_X__SHIFT				0
1704 
1705 #define GEN6_DEPTH_DW6_MOCS__MASK				0xf8000000
1706 #define GEN6_DEPTH_DW6_MOCS__SHIFT				27
1707 
1708 
1709 
1710 #define GEN7_DEPTH_DW1_TYPE__MASK				0xe0000000
1711 #define GEN7_DEPTH_DW1_TYPE__SHIFT				29
1712 #define GEN7_DEPTH_DW1_DEPTH_WRITE_ENABLE			(0x1 << 28)
1713 #define GEN7_DEPTH_DW1_STENCIL_WRITE_ENABLE			(0x1 << 27)
1714 #define GEN7_DEPTH_DW1_HIZ_ENABLE				(0x1 << 22)
1715 #define GEN7_DEPTH_DW1_FORMAT__MASK				0x001c0000
1716 #define GEN7_DEPTH_DW1_FORMAT__SHIFT				18
1717 #define GEN7_DEPTH_DW1_PITCH__MASK				0x0003ffff
1718 #define GEN7_DEPTH_DW1_PITCH__SHIFT				0
1719 
1720 
1721 #define GEN7_DEPTH_DW3_HEIGHT__MASK				0xfffc0000
1722 #define GEN7_DEPTH_DW3_HEIGHT__SHIFT				18
1723 #define GEN7_DEPTH_DW3_WIDTH__MASK				0x0003fff0
1724 #define GEN7_DEPTH_DW3_WIDTH__SHIFT				4
1725 #define GEN7_DEPTH_DW3_LOD__MASK				0x0000000f
1726 #define GEN7_DEPTH_DW3_LOD__SHIFT				0
1727 
1728 #define GEN7_DEPTH_DW4_DEPTH__MASK				0xffe00000
1729 #define GEN7_DEPTH_DW4_DEPTH__SHIFT				21
1730 #define GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__MASK			0x001ffc00
1731 #define GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT			10
1732 #define GEN7_DEPTH_DW4_MOCS__MASK				0x0000000f
1733 #define GEN7_DEPTH_DW4_MOCS__SHIFT				0
1734 
1735 #define GEN7_DEPTH_DW5_OFFSET_Y__MASK				0xffff0000
1736 #define GEN7_DEPTH_DW5_OFFSET_Y__SHIFT				16
1737 #define GEN7_DEPTH_DW5_OFFSET_X__MASK				0x0000ffff
1738 #define GEN7_DEPTH_DW5_OFFSET_X__SHIFT				0
1739 
1740 #define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__MASK			0xffe00000
1741 #define GEN7_DEPTH_DW6_RT_VIEW_EXTENT__SHIFT			21
1742 
1743 
1744 
1745 #define GEN8_DEPTH_DW1_TYPE__MASK				0xe0000000
1746 #define GEN8_DEPTH_DW1_TYPE__SHIFT				29
1747 #define GEN8_DEPTH_DW1_DEPTH_WRITE_ENABLE			(0x1 << 28)
1748 #define GEN8_DEPTH_DW1_STENCIL_WRITE_ENABLE			(0x1 << 27)
1749 #define GEN8_DEPTH_DW1_HIZ_ENABLE				(0x1 << 22)
1750 #define GEN8_DEPTH_DW1_FORMAT__MASK				0x001c0000
1751 #define GEN8_DEPTH_DW1_FORMAT__SHIFT				18
1752 #define GEN8_DEPTH_DW1_PITCH__MASK				0x0003ffff
1753 #define GEN8_DEPTH_DW1_PITCH__SHIFT				0
1754 
1755 
1756 
1757 #define GEN8_DEPTH_DW4_HEIGHT__MASK				0xfffc0000
1758 #define GEN8_DEPTH_DW4_HEIGHT__SHIFT				18
1759 #define GEN8_DEPTH_DW4_WIDTH__MASK				0x0003fff0
1760 #define GEN8_DEPTH_DW4_WIDTH__SHIFT				4
1761 #define GEN8_DEPTH_DW4_LOD__MASK				0x0000000f
1762 #define GEN8_DEPTH_DW4_LOD__SHIFT				0
1763 
1764 #define GEN8_DEPTH_DW5_DEPTH__MASK				0xffe00000
1765 #define GEN8_DEPTH_DW5_DEPTH__SHIFT				21
1766 #define GEN8_DEPTH_DW5_MIN_ARRAY_ELEMENT__MASK			0x001ffc00
1767 #define GEN8_DEPTH_DW5_MIN_ARRAY_ELEMENT__SHIFT			10
1768 #define GEN8_DEPTH_DW5_MOCS__MASK				0x0000007f
1769 #define GEN8_DEPTH_DW5_MOCS__SHIFT				0
1770 
1771 
1772 #define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__MASK			0xffe00000
1773 #define GEN8_DEPTH_DW7_RT_VIEW_EXTENT__SHIFT			21
1774 #define GEN8_DEPTH_DW7_QPITCH__MASK				0x00007fff
1775 #define GEN8_DEPTH_DW7_QPITCH__SHIFT				0
1776 #define GEN8_DEPTH_DW7_QPITCH__SHR				2
1777 
1778 #define GEN6_3DSTATE_POLY_STIPPLE_OFFSET__SIZE			2
1779 
1780 
1781 #define GEN6_POLY_STIPPLE_OFFSET_DW1_X__MASK			0x00001f00
1782 #define GEN6_POLY_STIPPLE_OFFSET_DW1_X__SHIFT			8
1783 #define GEN6_POLY_STIPPLE_OFFSET_DW1_Y__MASK			0x0000001f
1784 #define GEN6_POLY_STIPPLE_OFFSET_DW1_Y__SHIFT			0
1785 
1786 #define GEN6_3DSTATE_POLY_STIPPLE_PATTERN__SIZE			33
1787 
1788 
1789 
1790 #define GEN6_3DSTATE_LINE_STIPPLE__SIZE				3
1791 
1792 
1793 #define GEN6_LINE_STIPPLE_DW1_CURRENT_MODIFY_ENABLE		(0x1 << 31)
1794 #define GEN6_LINE_STIPPLE_DW1_CURRENT_REPEAT_COUNTER__MASK	0x3fe00000
1795 #define GEN6_LINE_STIPPLE_DW1_CURRENT_REPEAT_COUNTER__SHIFT	21
1796 #define GEN6_LINE_STIPPLE_DW1_CURRENT_STIPPLE_INDEX__MASK	0x000f0000
1797 #define GEN6_LINE_STIPPLE_DW1_CURRENT_STIPPLE_INDEX__SHIFT	16
1798 #define GEN6_LINE_STIPPLE_DW1_PATTERN__MASK			0x0000ffff
1799 #define GEN6_LINE_STIPPLE_DW1_PATTERN__SHIFT			0
1800 
1801 #define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__MASK	0xffff0000
1802 #define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT	16
1803 #define GEN6_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__RADIX	13
1804 #define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__MASK	0xffff8000
1805 #define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__SHIFT	15
1806 #define GEN7_LINE_STIPPLE_DW2_INVERSE_REPEAT_COUNT__RADIX	16
1807 #define GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__MASK		0x000001ff
1808 #define GEN6_LINE_STIPPLE_DW2_REPEAT_COUNT__SHIFT		0
1809 
1810 #define GEN6_3DSTATE_AA_LINE_PARAMETERS__SIZE			3
1811 
1812 
1813 #define GEN8_AA_LINE_DW1_POINT_BIAS__MASK			0xff000000
1814 #define GEN8_AA_LINE_DW1_POINT_BIAS__SHIFT			24
1815 #define GEN8_AA_LINE_DW1_POINT_BIAS__RADIX			8
1816 #define GEN6_AA_LINE_DW1_BIAS__MASK				0x00ff0000
1817 #define GEN6_AA_LINE_DW1_BIAS__SHIFT				16
1818 #define GEN6_AA_LINE_DW1_BIAS__RADIX				8
1819 #define GEN8_AA_LINE_DW1_POINT_SLOPE__MASK			0x0000ff00
1820 #define GEN8_AA_LINE_DW1_POINT_SLOPE__SHIFT			8
1821 #define GEN8_AA_LINE_DW1_POINT_SLOPE__RADIX			8
1822 #define GEN6_AA_LINE_DW1_SLOPE__MASK				0x000000ff
1823 #define GEN6_AA_LINE_DW1_SLOPE__SHIFT				0
1824 #define GEN6_AA_LINE_DW1_SLOPE__RADIX				8
1825 
1826 #define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__MASK			0xff000000
1827 #define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__SHIFT			24
1828 #define GEN8_AA_LINE_DW2_POINT_CAP_BIAS__RADIX			8
1829 #define GEN6_AA_LINE_DW2_CAP_BIAS__MASK				0x00ff0000
1830 #define GEN6_AA_LINE_DW2_CAP_BIAS__SHIFT			16
1831 #define GEN6_AA_LINE_DW2_CAP_BIAS__RADIX			8
1832 #define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__MASK			0x0000ff00
1833 #define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__SHIFT			8
1834 #define GEN8_AA_LINE_DW2_POINT_CAP_SLOPE__RADIX			8
1835 #define GEN6_AA_LINE_DW2_CAP_SLOPE__MASK			0x000000ff
1836 #define GEN6_AA_LINE_DW2_CAP_SLOPE__SHIFT			0
1837 #define GEN6_AA_LINE_DW2_CAP_SLOPE__RADIX			8
1838 
1839 #define GEN6_3DSTATE_GS_SVB_INDEX__SIZE				4
1840 
1841 
1842 #define GEN6_SVBI_DW1_INDEX__MASK				0x60000000
1843 #define GEN6_SVBI_DW1_INDEX__SHIFT				29
1844 #define GEN6_SVBI_DW1_LOAD_INTERNAL_VERTEX_COUNT		(0x1 << 0)
1845 
1846 
1847 
1848 #define GEN6_3DSTATE_MULTISAMPLE__SIZE				4
1849 
1850 
1851 #define GEN75_MULTISAMPLE_DW1_PIXEL_OFFSET_ENABLE		(0x1 << 5)
1852 #define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__MASK		0x00000010
1853 #define GEN6_MULTISAMPLE_DW1_PIXEL_LOCATION__SHIFT		4
1854 #define GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__MASK			0x0000000e
1855 #define GEN6_MULTISAMPLE_DW1_NUM_SAMPLES__SHIFT			1
1856 
1857 
1858 
1859 #define GEN8_3DSTATE_SAMPLE_PATTERN__SIZE			9
1860 
1861 
1862 
1863 
1864 
1865 #define GEN8_SAMPLE_PATTERN_DW8_1X__MASK			0x00ff0000
1866 #define GEN8_SAMPLE_PATTERN_DW8_1X__SHIFT			16
1867 #define GEN8_SAMPLE_PATTERN_DW8_2X__MASK			0x0000ffff
1868 #define GEN8_SAMPLE_PATTERN_DW8_2X__SHIFT			0
1869 
1870 #define GEN6_3DSTATE_STENCIL_BUFFER__SIZE			5
1871 
1872 
1873 #define GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE			(0x1 << 31)
1874 #define GEN6_STENCIL_DW1_MOCS__MASK				0x1e000000
1875 #define GEN6_STENCIL_DW1_MOCS__SHIFT				25
1876 #define GEN8_STENCIL_DW1_MOCS__MASK				0x1fc00000
1877 #define GEN8_STENCIL_DW1_MOCS__SHIFT				22
1878 #define GEN6_STENCIL_DW1_PITCH__MASK				0x0001ffff
1879 #define GEN6_STENCIL_DW1_PITCH__SHIFT				0
1880 
1881 
1882 
1883 #define GEN8_STENCIL_DW4_QPITCH__MASK				0x00007fff
1884 #define GEN8_STENCIL_DW4_QPITCH__SHIFT				0
1885 #define GEN8_STENCIL_DW4_QPITCH__SHR				2
1886 
1887 #define GEN6_3DSTATE_HIER_DEPTH_BUFFER__SIZE			5
1888 
1889 
1890 #define GEN6_HIZ_DW1_MOCS__MASK					0x1e000000
1891 #define GEN6_HIZ_DW1_MOCS__SHIFT				25
1892 #define GEN8_HIZ_DW1_MOCS__MASK					0xfe000000
1893 #define GEN8_HIZ_DW1_MOCS__SHIFT				25
1894 #define GEN6_HIZ_DW1_PITCH__MASK				0x0001ffff
1895 #define GEN6_HIZ_DW1_PITCH__SHIFT				0
1896 
1897 
1898 
1899 #define GEN8_HIZ_DW4_QPITCH__MASK				0x00007fff
1900 #define GEN8_HIZ_DW4_QPITCH__SHIFT				0
1901 #define GEN8_HIZ_DW4_QPITCH__SHR				2
1902 
1903 #define GEN6_3DSTATE_CLEAR_PARAMS__SIZE				3
1904 
1905 #define GEN6_CLEAR_PARAMS_DW0_VALID				(0x1 << 15)
1906 
1907 
1908 
1909 #define GEN7_CLEAR_PARAMS_DW2_VALID				(0x1 << 0)
1910 
1911 #define GEN6_3DPRIMITIVE__SIZE					7
1912 
1913 #define GEN6_3DPRIM_DW0_ACCESS__MASK				0x00008000
1914 #define GEN6_3DPRIM_DW0_ACCESS__SHIFT				15
1915 #define GEN6_3DPRIM_DW0_ACCESS_SEQUENTIAL			(0x0 << 15)
1916 #define GEN6_3DPRIM_DW0_ACCESS_RANDOM				(0x1 << 15)
1917 #define GEN6_3DPRIM_DW0_TYPE__MASK				0x00007c00
1918 #define GEN6_3DPRIM_DW0_TYPE__SHIFT				10
1919 #define GEN6_3DPRIM_DW0_USE_INTERNAL_VERTEX_COUNT		(0x1 << 9)
1920 
1921 
1922 
1923 
1924 
1925 
1926 
1927 #define GEN7_3DPRIM_DW0_INDIRECT_PARAM_ENABLE			(0x1 << 10)
1928 #define GEN75_3DPRIM_DW0_UAV_COHERENCY_REQUIRED			(0x1 << 9)
1929 #define GEN7_3DPRIM_DW0_PREDICATE_ENABLE			(0x1 << 8)
1930 
1931 #define GEN7_3DPRIM_DW1_END_OFFSET_ENABLE			(0x1 << 9)
1932 #define GEN7_3DPRIM_DW1_ACCESS__MASK				0x00000100
1933 #define GEN7_3DPRIM_DW1_ACCESS__SHIFT				8
1934 #define GEN7_3DPRIM_DW1_ACCESS_SEQUENTIAL			(0x0 << 8)
1935 #define GEN7_3DPRIM_DW1_ACCESS_RANDOM				(0x1 << 8)
1936 #define GEN7_3DPRIM_DW1_TYPE__MASK				0x0000003f
1937 #define GEN7_3DPRIM_DW1_TYPE__SHIFT				0
1938 
1939 
1940 
1941 
1942 
1943 
1944 
1945 #endif /* GEN_RENDER_3D_XML */
1946