1 #ifndef GEN_EU_ISA_XML 2 #define GEN_EU_ISA_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 https://github.com/olvaffe/envytools/ 8 git clone https://github.com/olvaffe/envytools.git 9 10 Copyright (C) 2014-2015 by the following authors: 11 - Chia-I Wu <olvaffe@gmail.com> (olv) 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice (including the 22 next paragraph) shall be included in all copies or substantial 23 portions of the Software. 24 25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 35 enum gen_eu_opcode { 36 GEN6_OPCODE_ILLEGAL = 0x0, 37 GEN6_OPCODE_MOV = 0x1, 38 GEN6_OPCODE_SEL = 0x2, 39 GEN6_OPCODE_MOVI = 0x3, 40 GEN6_OPCODE_NOT = 0x4, 41 GEN6_OPCODE_AND = 0x5, 42 GEN6_OPCODE_OR = 0x6, 43 GEN6_OPCODE_XOR = 0x7, 44 GEN6_OPCODE_SHR = 0x8, 45 GEN6_OPCODE_SHL = 0x9, 46 GEN6_OPCODE_DIM = 0xa, 47 GEN6_OPCODE_ASR = 0xc, 48 GEN6_OPCODE_CMP = 0x10, 49 GEN6_OPCODE_CMPN = 0x11, 50 GEN7_OPCODE_CSEL = 0x12, 51 GEN7_OPCODE_F32TO16 = 0x13, 52 GEN7_OPCODE_F16TO32 = 0x14, 53 GEN7_OPCODE_BFREV = 0x17, 54 GEN7_OPCODE_BFE = 0x18, 55 GEN7_OPCODE_BFI1 = 0x19, 56 GEN7_OPCODE_BFI2 = 0x1a, 57 GEN6_OPCODE_JMPI = 0x20, 58 GEN7_OPCODE_BRD = 0x21, 59 GEN6_OPCODE_IF = 0x22, 60 GEN7_OPCODE_BRC = 0x23, 61 GEN6_OPCODE_ELSE = 0x24, 62 GEN6_OPCODE_ENDIF = 0x25, 63 GEN6_OPCODE_CASE = 0x26, 64 GEN6_OPCODE_WHILE = 0x27, 65 GEN6_OPCODE_BREAK = 0x28, 66 GEN6_OPCODE_CONT = 0x29, 67 GEN6_OPCODE_HALT = 0x2a, 68 GEN75_OPCODE_CALLA = 0x2b, 69 GEN6_OPCODE_CALL = 0x2c, 70 GEN6_OPCODE_RETURN = 0x2d, 71 GEN8_OPCODE_GOTO = 0x2e, 72 GEN6_OPCODE_WAIT = 0x30, 73 GEN6_OPCODE_SEND = 0x31, 74 GEN6_OPCODE_SENDC = 0x32, 75 GEN6_OPCODE_MATH = 0x38, 76 GEN6_OPCODE_ADD = 0x40, 77 GEN6_OPCODE_MUL = 0x41, 78 GEN6_OPCODE_AVG = 0x42, 79 GEN6_OPCODE_FRC = 0x43, 80 GEN6_OPCODE_RNDU = 0x44, 81 GEN6_OPCODE_RNDD = 0x45, 82 GEN6_OPCODE_RNDE = 0x46, 83 GEN6_OPCODE_RNDZ = 0x47, 84 GEN6_OPCODE_MAC = 0x48, 85 GEN6_OPCODE_MACH = 0x49, 86 GEN6_OPCODE_LZD = 0x4a, 87 GEN7_OPCODE_FBH = 0x4b, 88 GEN7_OPCODE_FBL = 0x4c, 89 GEN7_OPCODE_CBIT = 0x4d, 90 GEN7_OPCODE_ADDC = 0x4e, 91 GEN7_OPCODE_SUBB = 0x4f, 92 GEN6_OPCODE_SAD2 = 0x50, 93 GEN6_OPCODE_SADA2 = 0x51, 94 GEN6_OPCODE_DP4 = 0x54, 95 GEN6_OPCODE_DPH = 0x55, 96 GEN6_OPCODE_DP3 = 0x56, 97 GEN6_OPCODE_DP2 = 0x57, 98 GEN6_OPCODE_LINE = 0x59, 99 GEN6_OPCODE_PLN = 0x5a, 100 GEN6_OPCODE_MAD = 0x5b, 101 GEN6_OPCODE_LRP = 0x5c, 102 GEN6_OPCODE_NOP = 0x7e, 103 }; 104 105 enum gen_eu_access_mode { 106 GEN6_ALIGN_1 = 0x0, 107 GEN6_ALIGN_16 = 0x1, 108 }; 109 110 enum gen_eu_mask_control { 111 GEN6_MASKCTRL_NORMAL = 0x0, 112 GEN6_MASKCTRL_NOMASK = 0x1, 113 }; 114 115 enum gen_eu_dependency_control { 116 GEN6_DEPCTRL_NORMAL = 0x0, 117 GEN6_DEPCTRL_NODDCLR = 0x1, 118 GEN6_DEPCTRL_NODDCHK = 0x2, 119 GEN6_DEPCTRL_NEITHER = 0x3, 120 }; 121 122 enum gen_eu_quarter_control { 123 GEN6_QTRCTRL_1Q = 0x0, 124 GEN6_QTRCTRL_2Q = 0x1, 125 GEN6_QTRCTRL_3Q = 0x2, 126 GEN6_QTRCTRL_4Q = 0x3, 127 GEN6_QTRCTRL_1H = 0x0, 128 GEN6_QTRCTRL_2H = 0x2, 129 }; 130 131 enum gen_eu_thread_control { 132 GEN6_THREADCTRL_NORMAL = 0x0, 133 GEN6_THREADCTRL_ATOMIC = 0x1, 134 GEN6_THREADCTRL_SWITCH = 0x2, 135 }; 136 137 enum gen_eu_predicate_control { 138 GEN6_PREDCTRL_NONE = 0x0, 139 GEN6_PREDCTRL_NORMAL = 0x1, 140 GEN6_PREDCTRL_ANYV = 0x2, 141 GEN6_PREDCTRL_ALLV = 0x3, 142 GEN6_PREDCTRL_ANY2H = 0x4, 143 GEN6_PREDCTRL_ALL2H = 0x5, 144 GEN6_PREDCTRL_X = 0x2, 145 GEN6_PREDCTRL_Y = 0x3, 146 GEN6_PREDCTRL_Z = 0x4, 147 GEN6_PREDCTRL_W = 0x5, 148 GEN6_PREDCTRL_ANY4H = 0x6, 149 GEN6_PREDCTRL_ALL4H = 0x7, 150 GEN6_PREDCTRL_ANY8H = 0x8, 151 GEN6_PREDCTRL_ALL8H = 0x9, 152 GEN6_PREDCTRL_ANY16H = 0xa, 153 GEN6_PREDCTRL_ALL16H = 0xb, 154 GEN7_PREDCTRL_ANY32H = 0xc, 155 GEN7_PREDCTRL_ALL32H = 0xd, 156 }; 157 158 enum gen_eu_exec_size { 159 GEN6_EXECSIZE_1 = 0x0, 160 GEN6_EXECSIZE_2 = 0x1, 161 GEN6_EXECSIZE_4 = 0x2, 162 GEN6_EXECSIZE_8 = 0x3, 163 GEN6_EXECSIZE_16 = 0x4, 164 GEN6_EXECSIZE_32 = 0x5, 165 }; 166 167 enum gen_eu_condition_modifier { 168 GEN6_COND_NONE = 0x0, 169 GEN6_COND_Z = 0x1, 170 GEN6_COND_NZ = 0x2, 171 GEN6_COND_G = 0x3, 172 GEN6_COND_GE = 0x4, 173 GEN6_COND_L = 0x5, 174 GEN6_COND_LE = 0x6, 175 GEN6_COND_O = 0x8, 176 GEN6_COND_U = 0x9, 177 }; 178 179 enum gen_eu_math_function_control { 180 GEN6_MATH_INV = 0x1, 181 GEN6_MATH_LOG = 0x2, 182 GEN6_MATH_EXP = 0x3, 183 GEN6_MATH_SQRT = 0x4, 184 GEN6_MATH_RSQ = 0x5, 185 GEN6_MATH_SIN = 0x6, 186 GEN6_MATH_COS = 0x7, 187 GEN6_MATH_FDIV = 0x9, 188 GEN6_MATH_POW = 0xa, 189 GEN6_MATH_INT_DIV = 0xb, 190 GEN6_MATH_INT_DIV_QUOTIENT = 0xc, 191 GEN6_MATH_INT_DIV_REMAINDER = 0xd, 192 GEN8_MATH_INVM = 0xe, 193 GEN8_MATH_RSQRTM = 0xf, 194 }; 195 196 enum gen_eu_shared_function_id { 197 GEN6_SFID_NULL = 0x0, 198 GEN6_SFID_SAMPLER = 0x2, 199 GEN6_SFID_GATEWAY = 0x3, 200 GEN6_SFID_DP_SAMPLER = 0x4, 201 GEN6_SFID_DP_RC = 0x5, 202 GEN6_SFID_URB = 0x6, 203 GEN6_SFID_SPAWNER = 0x7, 204 GEN6_SFID_VME = 0x8, 205 GEN6_SFID_DP_CC = 0x9, 206 GEN7_SFID_DP_DC0 = 0xa, 207 GEN7_SFID_PI = 0xb, 208 GEN75_SFID_DP_DC1 = 0xc, 209 }; 210 211 enum gen_eu_reg_file { 212 GEN6_FILE_ARF = 0x0, 213 GEN6_FILE_GRF = 0x1, 214 GEN6_FILE_MRF = 0x2, 215 GEN6_FILE_IMM = 0x3, 216 }; 217 218 enum gen_eu_reg_type { 219 GEN6_TYPE_UD = 0x0, 220 GEN6_TYPE_D = 0x1, 221 GEN6_TYPE_UW = 0x2, 222 GEN6_TYPE_W = 0x3, 223 GEN6_TYPE_UB = 0x4, 224 GEN6_TYPE_B = 0x5, 225 GEN7_TYPE_DF = 0x6, 226 GEN6_TYPE_F = 0x7, 227 GEN8_TYPE_UQ = 0x8, 228 GEN8_TYPE_Q = 0x9, 229 GEN8_TYPE_HF = 0xa, 230 GEN6_TYPE_UV_IMM = 0x4, 231 GEN6_TYPE_VF_IMM = 0x5, 232 GEN6_TYPE_V_IMM = 0x6, 233 GEN8_TYPE_DF_IMM = 0xa, 234 GEN8_TYPE_HF_IMM = 0xb, 235 GEN7_TYPE_F_3SRC = 0x0, 236 GEN7_TYPE_D_3SRC = 0x1, 237 GEN7_TYPE_UD_3SRC = 0x2, 238 GEN7_TYPE_DF_3SRC = 0x3, 239 }; 240 241 enum gen_eu_vertical_stride { 242 GEN6_VERTSTRIDE_0 = 0x0, 243 GEN6_VERTSTRIDE_1 = 0x1, 244 GEN6_VERTSTRIDE_2 = 0x2, 245 GEN6_VERTSTRIDE_4 = 0x3, 246 GEN6_VERTSTRIDE_8 = 0x4, 247 GEN6_VERTSTRIDE_16 = 0x5, 248 GEN6_VERTSTRIDE_32 = 0x6, 249 GEN6_VERTSTRIDE_VXH = 0xf, 250 }; 251 252 enum gen_eu_width { 253 GEN6_WIDTH_1 = 0x0, 254 GEN6_WIDTH_2 = 0x1, 255 GEN6_WIDTH_4 = 0x2, 256 GEN6_WIDTH_8 = 0x3, 257 GEN6_WIDTH_16 = 0x4, 258 }; 259 260 enum gen_eu_horizontal_stride { 261 GEN6_HORZSTRIDE_0 = 0x0, 262 GEN6_HORZSTRIDE_1 = 0x1, 263 GEN6_HORZSTRIDE_2 = 0x2, 264 GEN6_HORZSTRIDE_4 = 0x3, 265 }; 266 267 enum gen_eu_addressing_mode { 268 GEN6_ADDRMODE_DIRECT = 0x0, 269 GEN6_ADDRMODE_INDIRECT = 0x1, 270 }; 271 272 enum gen_eu_swizzle { 273 GEN6_SWIZZLE_X = 0x0, 274 GEN6_SWIZZLE_Y = 0x1, 275 GEN6_SWIZZLE_Z = 0x2, 276 GEN6_SWIZZLE_W = 0x3, 277 }; 278 279 enum gen_eu_arf_reg { 280 GEN6_ARF_NULL = 0x0, 281 GEN6_ARF_A0 = 0x10, 282 GEN6_ARF_ACC0 = 0x20, 283 GEN6_ARF_F0 = 0x30, 284 GEN6_ARF_SR0 = 0x70, 285 GEN6_ARF_CR0 = 0x80, 286 GEN6_ARF_N0 = 0x90, 287 GEN6_ARF_IP = 0xa0, 288 GEN6_ARF_TDR = 0xb0, 289 GEN7_ARF_TM0 = 0xc0, 290 }; 291 292 #define GEN6_INST_SATURATE (0x1 << 31) 293 #define GEN6_INST_DEBUGCTRL (0x1 << 30) 294 #define GEN6_INST_CMPTCTRL (0x1 << 29) 295 #define GEN8_INST_BRANCHCTRL (0x1 << 28) 296 #define GEN6_INST_ACCWRCTRL (0x1 << 28) 297 #define GEN6_INST_CONDMODIFIER__MASK 0x0f000000 298 #define GEN6_INST_CONDMODIFIER__SHIFT 24 299 #define GEN6_INST_SFID__MASK 0x0f000000 300 #define GEN6_INST_SFID__SHIFT 24 301 #define GEN6_INST_FC__MASK 0x0f000000 302 #define GEN6_INST_FC__SHIFT 24 303 #define GEN6_INST_EXECSIZE__MASK 0x00e00000 304 #define GEN6_INST_EXECSIZE__SHIFT 21 305 #define GEN6_INST_PREDINV (0x1 << 20) 306 #define GEN6_INST_PREDCTRL__MASK 0x000f0000 307 #define GEN6_INST_PREDCTRL__SHIFT 16 308 #define GEN6_INST_THREADCTRL__MASK 0x0000c000 309 #define GEN6_INST_THREADCTRL__SHIFT 14 310 #define GEN6_INST_QTRCTRL__MASK 0x00003000 311 #define GEN6_INST_QTRCTRL__SHIFT 12 312 #define GEN6_INST_DEPCTRL__MASK 0x00000c00 313 #define GEN6_INST_DEPCTRL__SHIFT 10 314 #define GEN6_INST_MASKCTRL__MASK 0x00000200 315 #define GEN6_INST_MASKCTRL__SHIFT 9 316 #define GEN8_INST_NIBCTRL (0x1 << 11) 317 #define GEN8_INST_DEPCTRL__MASK 0x00000600 318 #define GEN8_INST_DEPCTRL__SHIFT 9 319 #define GEN6_INST_ACCESSMODE__MASK 0x00000100 320 #define GEN6_INST_ACCESSMODE__SHIFT 8 321 #define GEN6_INST_OPCODE__MASK 0x0000007f 322 #define GEN6_INST_OPCODE__SHIFT 0 323 #define GEN6_INST_DST_ADDRMODE__MASK 0x80000000 324 #define GEN6_INST_DST_ADDRMODE__SHIFT 31 325 #define GEN6_INST_DST_HORZSTRIDE__MASK 0x60000000 326 #define GEN6_INST_DST_HORZSTRIDE__SHIFT 29 327 #define GEN6_INST_DST_REG__MASK 0x1fe00000 328 #define GEN6_INST_DST_REG__SHIFT 21 329 #define GEN6_INST_DST_SUBREG__MASK 0x001f0000 330 #define GEN6_INST_DST_SUBREG__SHIFT 16 331 #define GEN6_INST_DST_ADDR_SUBREG__MASK 0x1c000000 332 #define GEN6_INST_DST_ADDR_SUBREG__SHIFT 26 333 #define GEN6_INST_DST_ADDR_IMM__MASK 0x03ff0000 334 #define GEN6_INST_DST_ADDR_IMM__SHIFT 16 335 #define GEN8_INST_DST_ADDR_SUBREG__MASK 0x1e000000 336 #define GEN8_INST_DST_ADDR_SUBREG__SHIFT 25 337 #define GEN8_INST_DST_ADDR_IMM__MASK 0x01ff0000 338 #define GEN8_INST_DST_ADDR_IMM__SHIFT 16 339 #define GEN6_INST_DST_SUBREG_ALIGN16__MASK 0x00100000 340 #define GEN6_INST_DST_SUBREG_ALIGN16__SHIFT 20 341 #define GEN6_INST_DST_SUBREG_ALIGN16__SHR 4 342 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__MASK 0x03f00000 343 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHIFT 20 344 #define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHR 4 345 #define GEN8_INST_DST_ADDR_IMM_ALIGN16__MASK 0x01f00000 346 #define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHIFT 20 347 #define GEN8_INST_DST_ADDR_IMM_ALIGN16__SHR 4 348 #define GEN6_INST_DST_WRITEMASK__MASK 0x000f0000 349 #define GEN6_INST_DST_WRITEMASK__SHIFT 16 350 #define GEN7_INST_NIBCTRL (0x1 << 15) 351 #define GEN6_INST_SRC1_TYPE__MASK 0x00007000 352 #define GEN6_INST_SRC1_TYPE__SHIFT 12 353 #define GEN6_INST_SRC1_FILE__MASK 0x00000c00 354 #define GEN6_INST_SRC1_FILE__SHIFT 10 355 #define GEN6_INST_SRC0_TYPE__MASK 0x00000380 356 #define GEN6_INST_SRC0_TYPE__SHIFT 7 357 #define GEN6_INST_SRC0_FILE__MASK 0x00000060 358 #define GEN6_INST_SRC0_FILE__SHIFT 5 359 #define GEN6_INST_DST_TYPE__MASK 0x0000001c 360 #define GEN6_INST_DST_TYPE__SHIFT 2 361 #define GEN6_INST_DST_FILE__MASK 0x00000003 362 #define GEN6_INST_DST_FILE__SHIFT 0 363 #define GEN8_INST_DST_ADDR_IMM_BIT9__MASK 0x00008000 364 #define GEN8_INST_DST_ADDR_IMM_BIT9__SHIFT 15 365 #define GEN8_INST_DST_ADDR_IMM_BIT9__SHR 9 366 #define GEN8_INST_SRC0_TYPE__MASK 0x00007800 367 #define GEN8_INST_SRC0_TYPE__SHIFT 11 368 #define GEN8_INST_SRC0_FILE__MASK 0x00000600 369 #define GEN8_INST_SRC0_FILE__SHIFT 9 370 #define GEN8_INST_DST_TYPE__MASK 0x000001e0 371 #define GEN8_INST_DST_TYPE__SHIFT 5 372 #define GEN8_INST_DST_FILE__MASK 0x00000018 373 #define GEN8_INST_DST_FILE__SHIFT 3 374 #define GEN8_INST_MASKCTRL__MASK 0x00000004 375 #define GEN8_INST_MASKCTRL__SHIFT 2 376 #define GEN8_INST_FLAG_REG__MASK 0x00000002 377 #define GEN8_INST_FLAG_REG__SHIFT 1 378 #define GEN8_INST_FLAG_SUBREG__MASK 0x00000001 379 #define GEN8_INST_FLAG_SUBREG__SHIFT 0 380 #define GEN7_INST_FLAG_REG__MASK 0x04000000 381 #define GEN7_INST_FLAG_REG__SHIFT 26 382 #define GEN6_INST_FLAG_SUBREG__MASK 0x02000000 383 #define GEN6_INST_FLAG_SUBREG__SHIFT 25 384 #define GEN8_INST_SRC0_ADDR_IMM_BIT9__MASK 0x80000000 385 #define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHIFT 31 386 #define GEN8_INST_SRC0_ADDR_IMM_BIT9__SHR 9 387 #define GEN8_INST_SRC1_TYPE__MASK 0x78000000 388 #define GEN8_INST_SRC1_TYPE__SHIFT 27 389 #define GEN8_INST_SRC1_FILE__MASK 0x06000000 390 #define GEN8_INST_SRC1_FILE__SHIFT 25 391 #define GEN8_INST_SRC1_ADDR_IMM_BIT9__MASK 0x02000000 392 #define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHIFT 25 393 #define GEN8_INST_SRC1_ADDR_IMM_BIT9__SHR 9 394 #define GEN6_INST_SRC_VERTSTRIDE__MASK 0x01e00000 395 #define GEN6_INST_SRC_VERTSTRIDE__SHIFT 21 396 #define GEN6_INST_SRC_WIDTH__MASK 0x001c0000 397 #define GEN6_INST_SRC_WIDTH__SHIFT 18 398 #define GEN6_INST_SRC_HORZSTRIDE__MASK 0x00030000 399 #define GEN6_INST_SRC_HORZSTRIDE__SHIFT 16 400 #define GEN6_INST_SRC_SWIZZLE_W__MASK 0x000c0000 401 #define GEN6_INST_SRC_SWIZZLE_W__SHIFT 18 402 #define GEN6_INST_SRC_SWIZZLE_Z__MASK 0x00030000 403 #define GEN6_INST_SRC_SWIZZLE_Z__SHIFT 16 404 #define GEN6_INST_SRC_ADDRMODE__MASK 0x00008000 405 #define GEN6_INST_SRC_ADDRMODE__SHIFT 15 406 #define GEN6_INST_SRC_NEGATE (0x1 << 14) 407 #define GEN6_INST_SRC_ABSOLUTE (0x1 << 13) 408 #define GEN6_INST_SRC_REG__MASK 0x00001fe0 409 #define GEN6_INST_SRC_REG__SHIFT 5 410 #define GEN6_INST_SRC_SUBREG__MASK 0x0000001f 411 #define GEN6_INST_SRC_SUBREG__SHIFT 0 412 #define GEN6_INST_SRC_ADDR_SUBREG__MASK 0x00001c00 413 #define GEN6_INST_SRC_ADDR_SUBREG__SHIFT 10 414 #define GEN6_INST_SRC_ADDR_IMM__MASK 0x000003ff 415 #define GEN6_INST_SRC_ADDR_IMM__SHIFT 0 416 #define GEN8_INST_SRC_ADDR_SUBREG__MASK 0x00001e00 417 #define GEN8_INST_SRC_ADDR_SUBREG__SHIFT 9 418 #define GEN8_INST_SRC_ADDR_IMM__MASK 0x000001ff 419 #define GEN8_INST_SRC_ADDR_IMM__SHIFT 0 420 #define GEN6_INST_SRC_SUBREG_ALIGN16__MASK 0x00000010 421 #define GEN6_INST_SRC_SUBREG_ALIGN16__SHIFT 4 422 #define GEN6_INST_SRC_SUBREG_ALIGN16__SHR 4 423 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__MASK 0x000003f0 424 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHIFT 4 425 #define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHR 4 426 #define GEN8_INST_SRC_ADDR_IMM_ALIGN16__MASK 0x000001f0 427 #define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHIFT 4 428 #define GEN8_INST_SRC_ADDR_IMM_ALIGN16__SHR 4 429 #define GEN6_INST_SRC_SWIZZLE_Y__MASK 0x0000000c 430 #define GEN6_INST_SRC_SWIZZLE_Y__SHIFT 2 431 #define GEN6_INST_SRC_SWIZZLE_X__MASK 0x00000003 432 #define GEN6_INST_SRC_SWIZZLE_X__SHIFT 0 433 #define GEN6_3SRC_DST_REG__MASK 0xff000000 434 #define GEN6_3SRC_DST_REG__SHIFT 24 435 #define GEN6_3SRC_DST_SUBREG__MASK 0x00e00000 436 #define GEN6_3SRC_DST_SUBREG__SHIFT 21 437 #define GEN6_3SRC_DST_SUBREG__SHR 2 438 #define GEN6_3SRC_DST_WRITEMASK__MASK 0x001e0000 439 #define GEN6_3SRC_DST_WRITEMASK__SHIFT 17 440 #define GEN7_3SRC_NIBCTRL (0x1 << 15) 441 #define GEN7_3SRC_DST_TYPE__MASK 0x00003000 442 #define GEN7_3SRC_DST_TYPE__SHIFT 12 443 #define GEN7_3SRC_SRC_TYPE__MASK 0x00000c00 444 #define GEN7_3SRC_SRC_TYPE__SHIFT 10 445 #define GEN6_3SRC_SRC2_NEGATE (0x1 << 9) 446 #define GEN6_3SRC_SRC2_ABSOLUTE (0x1 << 8) 447 #define GEN6_3SRC_SRC1_NEGATE (0x1 << 7) 448 #define GEN6_3SRC_SRC1_ABSOLUTE (0x1 << 6) 449 #define GEN6_3SRC_SRC0_NEGATE (0x1 << 5) 450 #define GEN6_3SRC_SRC0_ABSOLUTE (0x1 << 4) 451 #define GEN7_3SRC_FLAG_REG__MASK 0x00000004 452 #define GEN7_3SRC_FLAG_REG__SHIFT 2 453 #define GEN6_3SRC_FLAG_SUBREG__MASK 0x00000002 454 #define GEN6_3SRC_FLAG_SUBREG__SHIFT 1 455 #define GEN6_3SRC_DST_FILE_MRF (0x1 << 0) 456 #define GEN8_3SRC_DST_TYPE__MASK 0x0001c000 457 #define GEN8_3SRC_DST_TYPE__SHIFT 14 458 #define GEN8_3SRC_SRC_TYPE__MASK 0x00003800 459 #define GEN8_3SRC_SRC_TYPE__SHIFT 11 460 #define GEN8_3SRC_SRC2_NEGATE (0x1 << 10) 461 #define GEN8_3SRC_SRC2_ABSOLUTE (0x1 << 9) 462 #define GEN8_3SRC_SRC1_NEGATE (0x1 << 8) 463 #define GEN8_3SRC_SRC1_ABSOLUTE (0x1 << 7) 464 #define GEN8_3SRC_SRC0_NEGATE (0x1 << 6) 465 #define GEN8_3SRC_SRC0_ABSOLUTE (0x1 << 5) 466 #define GEN8_3SRC_MASKCTRL__MASK 0x00000004 467 #define GEN8_3SRC_MASKCTRL__SHIFT 2 468 #define GEN8_3SRC_FLAG_REG__MASK 0x00000002 469 #define GEN8_3SRC_FLAG_REG__SHIFT 1 470 #define GEN8_3SRC_FLAG_SUBREG__MASK 0x00000001 471 #define GEN8_3SRC_FLAG_SUBREG__SHIFT 0 472 #define GEN6_3SRC_SRC_REG__MASK 0x000ff000 473 #define GEN6_3SRC_SRC_REG__SHIFT 12 474 #define GEN6_3SRC_SRC_SUBREG__MASK 0x00000e00 475 #define GEN6_3SRC_SRC_SUBREG__SHIFT 9 476 #define GEN6_3SRC_SRC_SUBREG__SHR 2 477 #define GEN6_3SRC_SRC_SWIZZLE_W__MASK 0x00000180 478 #define GEN6_3SRC_SRC_SWIZZLE_W__SHIFT 7 479 #define GEN6_3SRC_SRC_SWIZZLE_Z__MASK 0x00000060 480 #define GEN6_3SRC_SRC_SWIZZLE_Z__SHIFT 5 481 #define GEN6_3SRC_SRC_SWIZZLE_Y__MASK 0x00000018 482 #define GEN6_3SRC_SRC_SWIZZLE_Y__SHIFT 3 483 #define GEN6_3SRC_SRC_SWIZZLE_X__MASK 0x00000006 484 #define GEN6_3SRC_SRC_SWIZZLE_X__SHIFT 1 485 #define GEN6_3SRC_SRC_REPCTRL (0x1 << 0) 486 #define GEN6_COMPACT_SRC1_REG__MASK 0xff00000000000000ULL 487 #define GEN6_COMPACT_SRC1_REG__SHIFT 56 488 #define GEN6_COMPACT_SRC0_REG__MASK 0x00ff000000000000ULL 489 #define GEN6_COMPACT_SRC0_REG__SHIFT 48 490 #define GEN6_COMPACT_DST_REG__MASK 0x0000ff0000000000ULL 491 #define GEN6_COMPACT_DST_REG__SHIFT 40 492 #define GEN6_COMPACT_SRC1_INDEX__MASK 0x000000f800000000ULL 493 #define GEN6_COMPACT_SRC1_INDEX__SHIFT 35 494 #define GEN6_COMPACT_SRC0_INDEX__MASK 0x00000007c0000000ULL 495 #define GEN6_COMPACT_SRC0_INDEX__SHIFT 30 496 #define GEN6_COMPACT_CMPTCTRL (0x1 << 29) 497 #define GEN6_COMPACT_FLAG_SUBREG__MASK 0x10000000 498 #define GEN6_COMPACT_FLAG_SUBREG__SHIFT 28 499 #define GEN6_COMPACT_CONDMODIFIER__MASK 0x0f000000 500 #define GEN6_COMPACT_CONDMODIFIER__SHIFT 24 501 #define GEN6_COMPACT_ACCWRCTRL (0x1 << 23) 502 #define GEN6_COMPACT_SUBREG_INDEX__MASK 0x007c0000 503 #define GEN6_COMPACT_SUBREG_INDEX__SHIFT 18 504 #define GEN6_COMPACT_DATATYPE_INDEX__MASK 0x0003e000 505 #define GEN6_COMPACT_DATATYPE_INDEX__SHIFT 13 506 #define GEN6_COMPACT_CONTROL_INDEX__MASK 0x00001f00 507 #define GEN6_COMPACT_CONTROL_INDEX__SHIFT 8 508 #define GEN6_COMPACT_DEBUGCTRL (0x1 << 7) 509 #define GEN6_COMPACT_OPCODE__MASK 0x0000007f 510 #define GEN6_COMPACT_OPCODE__SHIFT 0 511 #define GEN8_COMPACT_3SRC_SRC2_REG__MASK 0xfe00000000000000ULL 512 #define GEN8_COMPACT_3SRC_SRC2_REG__SHIFT 57 513 #define GEN8_COMPACT_3SRC_SRC2_REG__SHR 1 514 #define GEN8_COMPACT_3SRC_SRC1_REG__MASK 0x01fc000000000000ULL 515 #define GEN8_COMPACT_3SRC_SRC1_REG__SHIFT 50 516 #define GEN8_COMPACT_3SRC_SRC1_REG__SHR 1 517 #define GEN8_COMPACT_3SRC_SRC0_REG__MASK 0x0003f80000000000ULL 518 #define GEN8_COMPACT_3SRC_SRC0_REG__SHIFT 43 519 #define GEN8_COMPACT_3SRC_SRC0_REG__SHR 1 520 #define GEN8_COMPACT_3SRC_SRC2_SUBREG__MASK 0x0000070000000000ULL 521 #define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHIFT 40 522 #define GEN8_COMPACT_3SRC_SRC2_SUBREG__SHR 2 523 #define GEN8_COMPACT_3SRC_SRC1_SUBREG__MASK 0x000000e000000000ULL 524 #define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHIFT 37 525 #define GEN8_COMPACT_3SRC_SRC1_SUBREG__SHR 2 526 #define GEN8_COMPACT_3SRC_SRC0_SUBREG__MASK 0x0000001c00000000ULL 527 #define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHIFT 34 528 #define GEN8_COMPACT_3SRC_SRC0_SUBREG__SHR 2 529 #define GEN8_COMPACT_3SRC_SRC2_REPCTRL (0x1ULL << 33) 530 #define GEN8_COMPACT_3SRC_SRC1_REPCTRL (0x1ULL << 32) 531 #define GEN8_COMPACT_3SRC_SATURATE (0x1 << 31) 532 #define GEN8_COMPACT_3SRC_DEBUGCTRL (0x1 << 30) 533 #define GEN8_COMPACT_3SRC_CMPTCTRL (0x1 << 29) 534 #define GEN8_COMPACT_3SRC_SRC0_REPCTRL (0x1 << 28) 535 #define GEN8_COMPACT_3SRC_DST_REG__MASK 0x0007f000 536 #define GEN8_COMPACT_3SRC_DST_REG__SHIFT 12 537 #define GEN8_COMPACT_3SRC_SOURCE_INDEX__MASK 0x00000c00 538 #define GEN8_COMPACT_3SRC_SOURCE_INDEX__SHIFT 10 539 #define GEN8_COMPACT_3SRC_CONTROL_INDEX__MASK 0x00000300 540 #define GEN8_COMPACT_3SRC_CONTROL_INDEX__SHIFT 8 541 #define GEN8_COMPACT_3SRC_OPCODE__MASK 0x0000007f 542 #define GEN8_COMPACT_3SRC_OPCODE__SHIFT 0 543 544 545 546 547 548 549 550 551 #define GEN6_3SRC_SRC_2__MASK 0x7ffffc0000000000ULL 552 #define GEN6_3SRC_SRC_2__SHIFT 42 553 #define GEN6_3SRC_SRC_1__MASK 0x000003ffffe00000ULL 554 #define GEN6_3SRC_SRC_1__SHIFT 21 555 #define GEN6_3SRC_SRC_0__MASK 0x001fffff 556 #define GEN6_3SRC_SRC_0__SHIFT 0 557 558 559 560 561 562 563 #endif /* GEN_EU_ISA_XML */ 564