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Searched refs:GPR32RegClass (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp279 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
298 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
312 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeInt()
349 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); in materializeFP()
355 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); in materializeFP()
357 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); in materializeFP()
368 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeGV()
390 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in materializeExternalCallSym()
610 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
616 unsigned TempReg = createResultReg(&Mips::GPR32RegClass); in emitCmp()
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DMipsMachineFunction.cpp52 : &Mips::GPR32RegClass; in getGlobalBaseReg()
61 : &Mips::GPR32RegClass; in createEhDataRegsFI()
73 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in createISRRegFI()
DMipsOptionRecord.h46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); in MipsRegInfoRecord()
64 const MCRegisterClass *GPR32RegClass; variable
DMipsSERegisterInfo.cpp57 return &Mips::GPR32RegClass; in intRegClass()
180 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
DMipsSEFrameLowering.cpp293 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64()
358 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; in expandExtractElementF64()
396 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()
567 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptPrologueStub()
696 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()
731 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass; in emitInterruptEpilogueStub()
870 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()
884 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()
DMipsSEInstrInfo.cpp86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
87 if (Mips::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
192 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
265 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in loadRegFromStack()
477 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
DMipsSubtarget.cpp139 &Mips::GPR64RegClass : &Mips::GPR32RegClass); in getCriticalPathRCs()
DMips16InstrInfo.cpp66 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
68 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
DMipsRegisterInfo.cpp57 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
DMipsAsmPrinter.cpp257 unsigned CPURegSize = Mips::GPR32RegClass.getSize(); in printSavedRegsBitmask()
276 } else if (Mips::GPR32RegClass.contains(Reg)) in printSavedRegsBitmask()
DMipsSEISelDAGToDAG.cpp144 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
DMipsSEISelLowering.cpp42 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); in MipsSETargetLowering()
2925 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitBPOSGE32()
2994 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in emitMSACBranchPseudo()
3226 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
DMipsISelLowering.cpp3517 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
3520 return std::make_pair(0U, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
3544 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass); in getRegForInlineAsmConstraint()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp344 : &AArch64::GPR32RegClass; in materializeInt()
377 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()
1253 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()
1296 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()
1338 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()
1379 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()
1676 RC = &AArch64::GPR32RegClass; in emitLogicalOp_rs()
1782 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1787 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
1792 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()
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DAArch64InstrInfo.cpp498 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
499 RC = &AArch64::GPR32RegClass; in insertSelect()
1303 return (AArch64::GPR32RegClass.contains(DstReg) || in isGPRCopy()
2145 AArch64::GPR32RegClass.contains(SrcReg)) { in copyPhysReg()
2150 if (AArch64::GPR32RegClass.contains(DestReg) && in copyPhysReg()
2206 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
2310 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
3408 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
3423 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
3445 RC = &AArch64::GPR32RegClass; in genAlternativeCodeSequence()
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DAArch64ISelLowering.cpp2510 RC = &AArch64::GPR32RegClass; in LowerFormalArguments()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsOptionRecord.cpp79 if (GPR32RegClass->contains(CurrentSubReg) || in SetPhysRegUsed()