Searched refs:GPR64RegClass (Results 1 – 19 of 19) sorted by relevance
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); in MipsRegInfoRecord()65 const MCRegisterClass *GPR64RegClass; variable
51 ? &Mips::GPR64RegClass in getGlobalBaseReg()60 ? &Mips::GPR64RegClass in createEhDataRegsFI()
60 return &Mips::GPR64RegClass; in intRegClass()180 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in eliminateFI()
145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. in copyPhysReg()146 if (Mips::GPR64RegClass.contains(SrcReg)) in copyPhysReg()155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. in copyPhysReg()194 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()267 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in loadRegFromStack()477 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in loadImmediate()
139 &Mips::GPR64RegClass : &Mips::GPR32RegClass); in getCriticalPathRCs()
396 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitPrologue()696 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitEpilogue()870 &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()884 ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in determineCalleeSaves()
57 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
144 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
45 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); in MipsSETargetLowering()3226 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in emitINSERT_DF_VIDX()
3522 return std::make_pair(0U, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()3546 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass); in getRegForInlineAsmConstraint()
343 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass in materializeInt()377 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in materializeFP()435 ResultReg = createResultReg(&AArch64::GPR64RegClass); in materializeGV()1253 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rr()1296 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_ri()1338 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rs()1379 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitAddSub_rx()1680 RC = &AArch64::GPR64RegClass; in emitLogicalOp_rs()1782 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()1787 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass; in emitLoad()[all …]
264 for (unsigned Reg : AArch64::GPR64RegClass) { in findScratchNonCalleeSaveRegister()907 assert(AArch64::GPR64RegClass.contains(RPI.Reg1) || in computeCalleeSaveRegisterPairs()909 RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1); in computeCalleeSaveRegisterPairs()914 if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) || in computeCalleeSaveRegisterPairs()1117 if (AArch64::GPR64RegClass.contains(Reg) && in determineCalleeSaves()1130 if (AArch64::GPR64RegClass.contains(PairedReg) && in determineCalleeSaves()1182 const TargetRegisterClass *RC = &AArch64::GPR64RegClass; in determineCalleeSaves()
173 return &AArch64::GPR64RegClass; in getPointerRegClass()179 return &AArch64::GPR64RegClass; // Only MSR & MRS copy NZCV. in getCrossCopyRegClass()402 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
120 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); in isGPR64()118 return AArch64::GPR64RegClass.contains(Reg); in isGPR64()
494 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()495 RC = &AArch64::GPR64RegClass; in insertSelect()1304 AArch64::GPR64RegClass.contains(DstReg)); in isGPRCopy()2132 AArch64::GPR64RegClass.contains(SrcReg)) { in copyPhysReg()2137 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()2158 assert(AArch64::GPR64RegClass.contains(SrcReg) && "Invalid NZCV copy"); in copyPhysReg()2167 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); in copyPhysReg()2216 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()2320 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()2467 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()[all …]
981 &AArch64::GPR64RegClass) in promoteLoadFromStore()
2512 RC = &AArch64::GPR64RegClass; in LowerFormalArguments()2661 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass); in saveVarArgRegisters()3336 if (AArch64::GPR64RegClass.contains(*I)) in LowerReturn()4423 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); in LowerRETURNADDR()10339 if (AArch64::GPR64RegClass.contains(*I)) in insertCopiesSplitCSR()10340 RC = &AArch64::GPR64RegClass; in insertCopiesSplitCSR()
80 GPR64RegClass->contains(CurrentSubReg)) in SetPhysRegUsed()