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Searched refs:GPRC (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.td370 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
375 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
376 [(set GPRC:$result,
377 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
383 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
402 def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
554 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
555 [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;
557 (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
558 [(set GPRC:$dst, (atomic_load_sub_8 xoaddr:$ptr, GPRC:$incr))]>;
[all …]
DPPCInstr64Bit.td264 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
267 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
399 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
401 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
402 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
404 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
406 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
408 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
422 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
424 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
[all …]
DPPCInstrAltivec.td196 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
199 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
202 (ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
205 (ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
209 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
212 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
215 (ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
218 (ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
581 def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM),
582 (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>;
[all …]
DPPCRegisterInfo.cpp371 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
372 const TargetRegisterClass *RC = LP64 ? G8RC : GPRC; in lowerDynamicAlloc()
464 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
465 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; in lowerCRSpilling()
DPPCFrameLowering.cpp774 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in processFunctionBeforeCalleeSavedScan() local
776 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; in processFunctionBeforeCalleeSavedScan()
DPPCRegisterInfo.td279 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaInstrInfo.td168 def CAS32 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$cmp, GPRC:$swp), "",
169 [(set GPRC:$dst, (atomic_cmp_swap_32 GPRC:$ptr, GPRC:$cmp, GPRC:$swp))], s_pseudo>;
170 def CAS64 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$cmp, GPRC:$swp), "",
171 [(set GPRC:$dst, (atomic_cmp_swap_64 GPRC:$ptr, GPRC:$cmp, GPRC:$swp))], s_pseudo>;
173 def LAS32 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$swp), "",
174 [(set GPRC:$dst, (atomic_load_add_32 GPRC:$ptr, GPRC:$swp))], s_pseudo>;
175 def LAS64 :PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$swp), "",
176 [(set GPRC:$dst, (atomic_load_add_64 GPRC:$ptr, GPRC:$swp))], s_pseudo>;
178 def SWAP32 : PseudoInstAlpha<(outs GPRC:$dst), (ins GPRC:$ptr, GPRC:$swp), "",
179 [(set GPRC:$dst, (atomic_swap_32 GPRC:$ptr, GPRC:$swp))], s_pseudo>;
[all …]
DAlphaInstrFormats.td59 let OutOperandList = (outs GPRC:$RA);
138 let OutOperandList = (outs GPRC:$RC);
139 let InOperandList = (ins GPRC:$RA, GPRC:$RB);
157 let OutOperandList = (outs GPRC:$RC);
158 let InOperandList = (ins GPRC:$RB);
175 let OutOperandList = (outs GPRC:$RDEST);
176 let InOperandList = (ins GPRC:$RCOND, GPRC:$RTRUE, GPRC:$RFALSE);
198 let OutOperandList = (outs GPRC:$RC);
199 let InOperandList = (ins GPRC:$RA, u8imm:$L);
216 let OutOperandList = (outs GPRC:$RDEST);
[all …]
DAlphaRegisterInfo.td113 def GPRC : RegisterClass<"Alpha", [i64], 64, (add
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp382 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerDynamicAlloc() local
383 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
432 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
440 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
502 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRSpilling() local
504 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
516 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
547 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in lowerCRRestore() local
549 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
561 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
[all …]
DPPCRegisterInfo.td233 def GPRC : RegisterClass<"PPC", [i32], 32, (add (sequence "R%u", 2, 12),
238 let AltOrders = [(add (sub GPRC, R2), R2)];
260 def GPRC_NOR0 : RegisterClass<"PPC", [i32], 32, (add (sub GPRC, R0), ZERO)> {
DPPCFrameLowering.cpp1691 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; in addScavengingSpillSlot() local
1693 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; in addScavengingSpillSlot()
DPPCInstrInfo.td408 def gprc : RegisterOperand<GPRC> {
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPURegisterInfo.td159 def GPRC : RegisterClass<"SPU", [i128], 128,
164 def R64C : RegisterClass<"SPU", [i64], 128, (add GPRC)>;
167 def R64FP : RegisterClass<"SPU", [f64], 128, (add GPRC)>;
170 def R32C : RegisterClass<"SPU", [i32], 128, (add GPRC)>;
173 def R32FP : RegisterClass<"SPU", [f32], 128, (add GPRC)>;
176 def R16C : RegisterClass<"SPU", [i16], 128, (add GPRC)>;
179 def R8C : RegisterClass<"SPU", [i8], 128, (add GPRC)>;
183 (add GPRC)>;
DSPU128InstrInfo.td40 def : Pat<(shl GPRC:$rA, R32C:$rB),
41 (SHLQBYBIr128 (SHLQBIr128 GPRC:$rA, R32C:$rB), R32C:$rB)>;
DSPUInstrInfo.td67 def r128: LoadDForm<GPRC>;
99 def r128: LoadAForm<GPRC>;
131 def r128: LoadXForm<GPRC>;
179 def r128: StoreDForm<GPRC>;
209 def r128: StoreAForm<GPRC>;
241 def r128: StoreXForm<GPRC>;
1230 def r128: ANDRegInst<GPRC>;
1292 def r128: ANDCRegInst<GPRC>;
1408 def r128: ORRegInst<GPRC>;
1495 def r128: LRRegInst<GPRC>;
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dasym-regclass-copy.ll5 ; This tests that the GPRC/GPRC_NOR0 intersection subclass relationship with
6 ; GPRC is handled correctly. When it was not, this test would assert.
/external/llvm/docs/
DCodeGenerator.rst1062 def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
1066 def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
1067 (STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;
/external/syslinux/gpxe/src/drivers/net/e1000/
De1000_hw.c6497 temp = E1000_READ_REG(hw, GPRC); in e1000_clear_hw_cntrs()