| /external/llvm/test/CodeGen/SystemZ/ |
| D | asm-17.ll | 6 ; Test i32 GPRs.
17 ; Test i64 GPRs.
63 ; Test clobbers of GPRs and CC.
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| D | args-08.ll | 5 ; Up to four integer return values fit into GPRs.
32 ; Up to four floating-point return values fit into GPRs.
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| D | fp-move-02.ll | 1 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10
11 ; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
57 ; Test 64-bit moves from GPRs to FPRs.
65 ; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type,
80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
90 ; Test 64-bit moves from FPRs to GPRs.
98 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
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| D | frame-05.ll | 1 ; Test saving and restoring of call-saved GPRs.
5 ; This function should require all GPRs, but no other spill slots. The caller
81 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
188 ; This function should use all call-clobbered GPRs but no call-saved ones.
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| D | int-move-01.ll | 1 ; Test moves between GPRs.
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| D | frame-06.ll | 7 ; This function should require all GPRs, but no other spill slots. The caller
78 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
185 ; This function should use all call-clobbered GPRs but no call-saved ones.
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| D | args-07.ll | 5 ; Up to four integer return values fit into GPRs.
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| D | fp-move-10.ll | 1 ; Test moves between FPRs and GPRs for z13 and above.
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| /external/libunwind_llvm/src/ |
| D | Registers.hpp | 67 struct GPRs { struct in libunwind::Registers_x86
86 GPRs _registers;
273 struct GPRs { struct in libunwind::Registers_x86_64
296 GPRs _registers;
1079 struct GPRs { struct in libunwind::Registers_arm64
1088 GPRs _registers;
1100 static_assert(sizeof(GPRs) == 0x110, in Registers_arm64()
1103 static_cast<const uint8_t *>(registers) + sizeof(GPRs), in Registers_arm64()
1371 struct GPRs { struct in libunwind::Registers_arm
1393 GPRs _registers;
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | mmx-copy-gprs.ll | 6 ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
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| D | mmx-arg-passing.ll | 11 ; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
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| /external/llvm/test/CodeGen/X86/ |
| D | mmx-copy-gprs.ll | 6 ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
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| D | mmx-arg-passing.ll | 9 ; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
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| D | mmx-arg-passing-x86-64.ll | 5 ; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
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| /external/llvm/test/CodeGen/Thumb/ |
| D | 2011-06-16-NoGPRs.ll | 5 ; register, but we cannot have live GPRs in thumb mode because we don't know how
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/ |
| D | 2011-06-16-NoGPRs.ll | 5 ; register, but we cannot have live GPRs in thumb mode because we don't know how
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | ppc64-align-long-double.ll | 5 ; argument comes in in GPR3; GPR4 is skipped; GPRs 5 and 6 contain
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| /external/python/cpython2/Modules/_ctypes/libffi/src/powerpc/ |
| D | darwin_closure.S | 39 ; Define some pseudo-opcodes for size-independent load & store of GPRs ...
45 ; ... and the size of GPRs and their storage indicator.
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| D | darwin.S | 36 ; Define some pseudo-opcodes for size-independent load & store of GPRs ...
43 ; ... and the size of GPRs and their storage indicator.
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstX8664.def | 21 // Scratch GPRs: rax, rcx, rdx, rsi, rdi, r8, r9, r10, r11
22 // Callee-save GPRs: rbx, rbp, r12, r13, r14, r15
26 // Scratch GPRs: rax, rcx, rdx, r8, r9, r10, r11
27 // Callee-save GPRs: rbx, rbp, rsi, rdi, r12, r13, r14, r15
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| /external/llvm/test/CodeGen/Hexagon/ |
| D | avoid-predspill.ll | 3 ; This checks that predicate registers are moved to GPRs instead of spilling
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| /external/llvm/lib/Target/ARM/ |
| D | ARMRegisterInfo.td | 206 // GPRs without the PC. Some ARM instructions do not allow the PC in
216 // GPRs without the PC but with APSR. Some instructions allow accessing the
346 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
347 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
352 // Register class representing a pair of even-odd GPRs.
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| /external/llvm/test/CodeGen/ARM/ |
| D | 2013-04-16-AAPCS-C5-vs-VFP.ll | 4 ; Our purpose: make NSAA != SP, and only after start to use GPRs, then pass
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMCallingConv.td | 34 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
113 // i64/f64 is passed in even pairs of GPRs
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| /external/swiftshader/third_party/subzero/pydir/ |
| D | gen_arm32_reg_tables.py | 81 GPRs = [ variable
199 RegClasses = [('GPR', GPRs), ('I64PAIR', I64Pairs), ('FP32', FP32),
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