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1 /*
2  *
3  * This file is provided under a dual BSD/GPLv2 license.  When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * GPL LICENSE SUMMARY
7  *
8  * Copyright(c) 2015 Intel Corporation.
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of version 2 of the GNU General Public License as
12  * published by the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but
15  * WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17  * General Public License for more details.
18  *
19  * BSD LICENSE
20  *
21  * Copyright(c) 2015 Intel Corporation.
22  *
23  * Redistribution and use in source and binary forms, with or without
24  * modification, are permitted provided that the following conditions
25  * are met:
26  *
27  *  - Redistributions of source code must retain the above copyright
28  *    notice, this list of conditions and the following disclaimer.
29  *  - Redistributions in binary form must reproduce the above copyright
30  *    notice, this list of conditions and the following disclaimer in
31  *    the documentation and/or other materials provided with the
32  *    distribution.
33  *  - Neither the name of Intel Corporation nor the names of its
34  *    contributors may be used to endorse or promote products derived
35  *    from this software without specific prior written permission.
36  *
37  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48  *
49  */
50 
51 /*
52  * This file contains defines, structures, etc. that are used
53  * to communicate between kernel and user code.
54  */
55 
56 #ifndef _LINUX__HFI1_USER_H
57 #define _LINUX__HFI1_USER_H
58 
59 #include <linux/types.h>
60 
61 /*
62  * This version number is given to the driver by the user code during
63  * initialization in the spu_userversion field of hfi1_user_info, so
64  * the driver can check for compatibility with user code.
65  *
66  * The major version changes when data structures change in an incompatible
67  * way. The driver must be the same for initialization to succeed.
68  */
69 #define HFI1_USER_SWMAJOR 6
70 
71 /*
72  * Minor version differences are always compatible
73  * a within a major version, however if user software is larger
74  * than driver software, some new features and/or structure fields
75  * may not be implemented; the user code must deal with this if it
76  * cares, or it must abort after initialization reports the difference.
77  */
78 #define HFI1_USER_SWMINOR 3
79 
80 /*
81  * We will encode the major/minor inside a single 32bit version number.
82  */
83 #define HFI1_SWMAJOR_SHIFT 16
84 
85 /*
86  * Set of HW and driver capability/feature bits.
87  * These bit values are used to configure enabled/disabled HW and
88  * driver features. The same set of bits are communicated to user
89  * space.
90  */
91 #define HFI1_CAP_DMA_RTAIL        (1UL <<  0) /* Use DMA'ed RTail value */
92 #define HFI1_CAP_SDMA             (1UL <<  1) /* Enable SDMA support */
93 #define HFI1_CAP_SDMA_AHG         (1UL <<  2) /* Enable SDMA AHG support */
94 #define HFI1_CAP_EXTENDED_PSN     (1UL <<  3) /* Enable Extended PSN support */
95 #define HFI1_CAP_HDRSUPP          (1UL <<  4) /* Enable Header Suppression */
96 /* 1UL << 5 unused */
97 #define HFI1_CAP_USE_SDMA_HEAD    (1UL <<  6) /* DMA Hdr Q tail vs. use CSR */
98 #define HFI1_CAP_MULTI_PKT_EGR    (1UL <<  7) /* Enable multi-packet Egr buffs*/
99 #define HFI1_CAP_NODROP_RHQ_FULL  (1UL <<  8) /* Don't drop on Hdr Q full */
100 #define HFI1_CAP_NODROP_EGR_FULL  (1UL <<  9) /* Don't drop on EGR buffs full */
101 #define HFI1_CAP_TID_UNMAP        (1UL << 10) /* Disable Expected TID caching */
102 #define HFI1_CAP_PRINT_UNIMPL     (1UL << 11) /* Show for unimplemented feats */
103 #define HFI1_CAP_ALLOW_PERM_JKEY  (1UL << 12) /* Allow use of permissive JKEY */
104 #define HFI1_CAP_NO_INTEGRITY     (1UL << 13) /* Enable ctxt integrity checks */
105 #define HFI1_CAP_PKEY_CHECK       (1UL << 14) /* Enable ctxt PKey checking */
106 #define HFI1_CAP_STATIC_RATE_CTRL (1UL << 15) /* Allow PBC.StaticRateControl */
107 /* 1UL << 16 unused */
108 #define HFI1_CAP_SDMA_HEAD_CHECK  (1UL << 17) /* SDMA head checking */
109 #define HFI1_CAP_EARLY_CREDIT_RETURN (1UL << 18) /* early credit return */
110 
111 #define HFI1_RCVHDR_ENTSIZE_2    (1UL << 0)
112 #define HFI1_RCVHDR_ENTSIZE_16   (1UL << 1)
113 #define HFI1_RCVDHR_ENTSIZE_32   (1UL << 2)
114 
115 /* User commands. */
116 #define HFI1_CMD_ASSIGN_CTXT     1	/* allocate HFI and context */
117 #define HFI1_CMD_CTXT_INFO       2	/* find out what resources we got */
118 #define HFI1_CMD_USER_INFO       3	/* set up userspace */
119 #define HFI1_CMD_TID_UPDATE      4	/* update expected TID entries */
120 #define HFI1_CMD_TID_FREE        5	/* free expected TID entries */
121 #define HFI1_CMD_CREDIT_UPD      6	/* force an update of PIO credit */
122 
123 #define HFI1_CMD_RECV_CTRL       8	/* control receipt of packets */
124 #define HFI1_CMD_POLL_TYPE       9	/* set the kind of polling we want */
125 #define HFI1_CMD_ACK_EVENT       10	/* ack & clear user status bits */
126 #define HFI1_CMD_SET_PKEY        11     /* set context's pkey */
127 #define HFI1_CMD_CTXT_RESET      12     /* reset context's HW send context */
128 #define HFI1_CMD_TID_INVAL_READ  13     /* read TID cache invalidations */
129 #define HFI1_CMD_GET_VERS	 14	/* get the version of the user cdev */
130 
131 /*
132  * User IOCTLs can not go above 128 if they do then see common.h and change the
133  * base for the snoop ioctl
134  */
135 #define IB_IOCTL_MAGIC 0x1b /* See Documentation/ioctl/ioctl-number.txt */
136 
137 /*
138  * Make the ioctls occupy the last 0xf0-0xff portion of the IB range
139  */
140 #define __NUM(cmd) (HFI1_CMD_##cmd + 0xe0)
141 
142 struct hfi1_cmd;
143 #define HFI1_IOCTL_ASSIGN_CTXT \
144 	_IOWR(IB_IOCTL_MAGIC, __NUM(ASSIGN_CTXT), struct hfi1_user_info)
145 #define HFI1_IOCTL_CTXT_INFO \
146 	_IOW(IB_IOCTL_MAGIC, __NUM(CTXT_INFO), struct hfi1_ctxt_info)
147 #define HFI1_IOCTL_USER_INFO \
148 	_IOW(IB_IOCTL_MAGIC, __NUM(USER_INFO), struct hfi1_base_info)
149 #define HFI1_IOCTL_TID_UPDATE \
150 	_IOWR(IB_IOCTL_MAGIC, __NUM(TID_UPDATE), struct hfi1_tid_info)
151 #define HFI1_IOCTL_TID_FREE \
152 	_IOWR(IB_IOCTL_MAGIC, __NUM(TID_FREE), struct hfi1_tid_info)
153 #define HFI1_IOCTL_CREDIT_UPD \
154 	_IO(IB_IOCTL_MAGIC, __NUM(CREDIT_UPD))
155 #define HFI1_IOCTL_RECV_CTRL \
156 	_IOW(IB_IOCTL_MAGIC, __NUM(RECV_CTRL), int)
157 #define HFI1_IOCTL_POLL_TYPE \
158 	_IOW(IB_IOCTL_MAGIC, __NUM(POLL_TYPE), int)
159 #define HFI1_IOCTL_ACK_EVENT \
160 	_IOW(IB_IOCTL_MAGIC, __NUM(ACK_EVENT), unsigned long)
161 #define HFI1_IOCTL_SET_PKEY \
162 	_IOW(IB_IOCTL_MAGIC, __NUM(SET_PKEY), __u16)
163 #define HFI1_IOCTL_CTXT_RESET \
164 	_IO(IB_IOCTL_MAGIC, __NUM(CTXT_RESET))
165 #define HFI1_IOCTL_TID_INVAL_READ \
166 	_IOWR(IB_IOCTL_MAGIC, __NUM(TID_INVAL_READ), struct hfi1_tid_info)
167 #define HFI1_IOCTL_GET_VERS \
168 	_IOR(IB_IOCTL_MAGIC, __NUM(GET_VERS), int)
169 
170 #define _HFI1_EVENT_FROZEN_BIT         0
171 #define _HFI1_EVENT_LINKDOWN_BIT       1
172 #define _HFI1_EVENT_LID_CHANGE_BIT     2
173 #define _HFI1_EVENT_LMC_CHANGE_BIT     3
174 #define _HFI1_EVENT_SL2VL_CHANGE_BIT   4
175 #define _HFI1_EVENT_TID_MMU_NOTIFY_BIT 5
176 #define _HFI1_MAX_EVENT_BIT _HFI1_EVENT_TID_MMU_NOTIFY_BIT
177 
178 #define HFI1_EVENT_FROZEN            (1UL << _HFI1_EVENT_FROZEN_BIT)
179 #define HFI1_EVENT_LINKDOWN          (1UL << _HFI1_EVENT_LINKDOWN_BIT)
180 #define HFI1_EVENT_LID_CHANGE        (1UL << _HFI1_EVENT_LID_CHANGE_BIT)
181 #define HFI1_EVENT_LMC_CHANGE        (1UL << _HFI1_EVENT_LMC_CHANGE_BIT)
182 #define HFI1_EVENT_SL2VL_CHANGE      (1UL << _HFI1_EVENT_SL2VL_CHANGE_BIT)
183 #define HFI1_EVENT_TID_MMU_NOTIFY    (1UL << _HFI1_EVENT_TID_MMU_NOTIFY_BIT)
184 
185 /*
186  * These are the status bits readable (in ASCII form, 64bit value)
187  * from the "status" sysfs file.  For binary compatibility, values
188  * must remain as is; removed states can be reused for different
189  * purposes.
190  */
191 #define HFI1_STATUS_INITTED       0x1    /* basic initialization done */
192 /* Chip has been found and initialized */
193 #define HFI1_STATUS_CHIP_PRESENT 0x20
194 /* IB link is at ACTIVE, usable for data traffic */
195 #define HFI1_STATUS_IB_READY     0x40
196 /* link is configured, LID, MTU, etc. have been set */
197 #define HFI1_STATUS_IB_CONF      0x80
198 /* A Fatal hardware error has occurred. */
199 #define HFI1_STATUS_HWERROR     0x200
200 
201 /*
202  * Number of supported shared contexts.
203  * This is the maximum number of software contexts that can share
204  * a hardware send/receive context.
205  */
206 #define HFI1_MAX_SHARED_CTXTS 8
207 
208 /*
209  * Poll types
210  */
211 #define HFI1_POLL_TYPE_ANYRCV     0x0
212 #define HFI1_POLL_TYPE_URGENT     0x1
213 
214 /*
215  * This structure is passed to the driver to tell it where
216  * user code buffers are, sizes, etc.   The offsets and sizes of the
217  * fields must remain unchanged, for binary compatibility.  It can
218  * be extended, if userversion is changed so user code can tell, if needed
219  */
220 struct hfi1_user_info {
221 	/*
222 	 * version of user software, to detect compatibility issues.
223 	 * Should be set to HFI1_USER_SWVERSION.
224 	 */
225 	__u32 userversion;
226 	__u32 pad;
227 	/*
228 	 * If two or more processes wish to share a context, each process
229 	 * must set the subcontext_cnt and subcontext_id to the same
230 	 * values.  The only restriction on the subcontext_id is that
231 	 * it be unique for a given node.
232 	 */
233 	__u16 subctxt_cnt;
234 	__u16 subctxt_id;
235 	/* 128bit UUID passed in by PSM. */
236 	__u8 uuid[16];
237 };
238 
239 struct hfi1_ctxt_info {
240 	__u64 runtime_flags;    /* chip/drv runtime flags (HFI1_CAP_*) */
241 	__u32 rcvegr_size;      /* size of each eager buffer */
242 	__u16 num_active;       /* number of active units */
243 	__u16 unit;             /* unit (chip) assigned to caller */
244 	__u16 ctxt;             /* ctxt on unit assigned to caller */
245 	__u16 subctxt;          /* subctxt on unit assigned to caller */
246 	__u16 rcvtids;          /* number of Rcv TIDs for this context */
247 	__u16 credits;          /* number of PIO credits for this context */
248 	__u16 numa_node;        /* NUMA node of the assigned device */
249 	__u16 rec_cpu;          /* cpu # for affinity (0xffff if none) */
250 	__u16 send_ctxt;        /* send context in use by this user context */
251 	__u16 egrtids;          /* number of RcvArray entries for Eager Rcvs */
252 	__u16 rcvhdrq_cnt;      /* number of RcvHdrQ entries */
253 	__u16 rcvhdrq_entsize;  /* size (in bytes) for each RcvHdrQ entry */
254 	__u16 sdma_ring_size;   /* number of entries in SDMA request ring */
255 };
256 
257 struct hfi1_tid_info {
258 	/* virtual address of first page in transfer */
259 	__u64 vaddr;
260 	/* pointer to tid array. this array is big enough */
261 	__u64 tidlist;
262 	/* number of tids programmed by this request */
263 	__u32 tidcnt;
264 	/* length of transfer buffer programmed by this request */
265 	__u32 length;
266 };
267 
268 enum hfi1_sdma_comp_state {
269 	FREE = 0,
270 	QUEUED,
271 	COMPLETE,
272 	ERROR
273 };
274 
275 /*
276  * SDMA completion ring entry
277  */
278 struct hfi1_sdma_comp_entry {
279 	__u32 status;
280 	__u32 errcode;
281 };
282 
283 /*
284  * Device status and notifications from driver to user-space.
285  */
286 struct hfi1_status {
287 	__u64 dev;      /* device/hw status bits */
288 	__u64 port;     /* port state and status bits */
289 	char freezemsg[0];
290 };
291 
292 /*
293  * This structure is returned by the driver immediately after
294  * open to get implementation-specific info, and info specific to this
295  * instance.
296  *
297  * This struct must have explicit pad fields where type sizes
298  * may result in different alignments between 32 and 64 bit
299  * programs, since the 64 bit * bit kernel requires the user code
300  * to have matching offsets
301  */
302 struct hfi1_base_info {
303 	/* version of hardware, for feature checking. */
304 	__u32 hw_version;
305 	/* version of software, for feature checking. */
306 	__u32 sw_version;
307 	/* Job key */
308 	__u16 jkey;
309 	__u16 padding1;
310 	/*
311 	 * The special QP (queue pair) value that identifies PSM
312 	 * protocol packet from standard IB packets.
313 	 */
314 	__u32 bthqp;
315 	/* PIO credit return address, */
316 	__u64 sc_credits_addr;
317 	/*
318 	 * Base address of write-only pio buffers for this process.
319 	 * Each buffer has sendpio_credits*64 bytes.
320 	 */
321 	__u64 pio_bufbase_sop;
322 	/*
323 	 * Base address of write-only pio buffers for this process.
324 	 * Each buffer has sendpio_credits*64 bytes.
325 	 */
326 	__u64 pio_bufbase;
327 	/* address where receive buffer queue is mapped into */
328 	__u64 rcvhdr_bufbase;
329 	/* base address of Eager receive buffers. */
330 	__u64 rcvegr_bufbase;
331 	/* base address of SDMA completion ring */
332 	__u64 sdma_comp_bufbase;
333 	/*
334 	 * User register base for init code, not to be used directly by
335 	 * protocol or applications.  Always maps real chip register space.
336 	 * the register addresses are:
337 	 * ur_rcvhdrhead, ur_rcvhdrtail, ur_rcvegrhead, ur_rcvegrtail,
338 	 * ur_rcvtidflow
339 	 */
340 	__u64 user_regbase;
341 	/* notification events */
342 	__u64 events_bufbase;
343 	/* status page */
344 	__u64 status_bufbase;
345 	/* rcvhdrtail update */
346 	__u64 rcvhdrtail_base;
347 	/*
348 	 * shared memory pages for subctxts if ctxt is shared; these cover
349 	 * all the processes in the group sharing a single context.
350 	 * all have enough space for the num_subcontexts value on this job.
351 	 */
352 	__u64 subctxt_uregbase;
353 	__u64 subctxt_rcvegrbuf;
354 	__u64 subctxt_rcvhdrbuf;
355 };
356 
357 enum sdma_req_opcode {
358 	EXPECTED = 0,
359 	EAGER
360 };
361 
362 #define HFI1_SDMA_REQ_VERSION_MASK 0xF
363 #define HFI1_SDMA_REQ_VERSION_SHIFT 0x0
364 #define HFI1_SDMA_REQ_OPCODE_MASK 0xF
365 #define HFI1_SDMA_REQ_OPCODE_SHIFT 0x4
366 #define HFI1_SDMA_REQ_IOVCNT_MASK 0xFF
367 #define HFI1_SDMA_REQ_IOVCNT_SHIFT 0x8
368 
369 struct sdma_req_info {
370 	/*
371 	 * bits 0-3 - version (currently unused)
372 	 * bits 4-7 - opcode (enum sdma_req_opcode)
373 	 * bits 8-15 - io vector count
374 	 */
375 	__u16 ctrl;
376 	/*
377 	 * Number of fragments contained in this request.
378 	 * User-space has already computed how many
379 	 * fragment-sized packet the user buffer will be
380 	 * split into.
381 	 */
382 	__u16 npkts;
383 	/*
384 	 * Size of each fragment the user buffer will be
385 	 * split into.
386 	 */
387 	__u16 fragsize;
388 	/*
389 	 * Index of the slot in the SDMA completion ring
390 	 * this request should be using. User-space is
391 	 * in charge of managing its own ring.
392 	 */
393 	__u16 comp_idx;
394 } __packed;
395 
396 /*
397  * SW KDETH header.
398  * swdata is SW defined portion.
399  */
400 struct hfi1_kdeth_header {
401 	__le32 ver_tid_offset;
402 	__le16 jkey;
403 	__le16 hcrc;
404 	__le32 swdata[7];
405 } __packed;
406 
407 /*
408  * Structure describing the headers that User space uses. The
409  * structure above is a subset of this one.
410  */
411 struct hfi1_pkt_header {
412 	__le16 pbc[4];
413 	__be16 lrh[4];
414 	__be32 bth[3];
415 	struct hfi1_kdeth_header kdeth;
416 } __packed;
417 
418 
419 /*
420  * The list of usermode accessible registers.
421  */
422 enum hfi1_ureg {
423 	/* (RO)  DMA RcvHdr to be used next. */
424 	ur_rcvhdrtail = 0,
425 	/* (RW)  RcvHdr entry to be processed next by host. */
426 	ur_rcvhdrhead = 1,
427 	/* (RO)  Index of next Eager index to use. */
428 	ur_rcvegrindextail = 2,
429 	/* (RW)  Eager TID to be processed next */
430 	ur_rcvegrindexhead = 3,
431 	/* (RO)  Receive Eager Offset Tail */
432 	ur_rcvegroffsettail = 4,
433 	/* For internal use only; max register number. */
434 	ur_maxreg,
435 	/* (RW)  Receive TID flow table */
436 	ur_rcvtidflowtable = 256
437 };
438 
439 #endif /* _LINIUX__HFI1_USER_H */
440