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Searched refs:I915_TILING_X (Results 1 – 20 of 20) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_tex_layout.c621 return I915_TILING_X; in brw_miptree_choose_tiling()
630 return I915_TILING_X; in brw_miptree_choose_tiling()
646 return I915_TILING_X; in brw_miptree_choose_tiling()
649 return I915_TILING_Y | I915_TILING_X; in brw_miptree_choose_tiling()
Dintel_pixel_read.c132 (irb->mt->tiling != I915_TILING_X && in intel_readpixels_tiled_memcpy()
Dintel_tex_subimage.c133 (image->mt->tiling != I915_TILING_X && in intel_texsubimage_tiled_memcpy()
Dintel_tiled_memcpy.c646 if (tiling == I915_TILING_X) { in linear_to_tiled()
737 if (tiling == I915_TILING_X) { in tiled_to_linear()
Dintel_mipmap_tree.c639 if (mt->tiling == (I915_TILING_Y | I915_TILING_X)) in miptree_create()
707 mt->tiling = I915_TILING_X; in intel_miptree_create()
1159 case I915_TILING_X: in intel_get_tile_dims()
1240 case I915_TILING_X: in intel_miptree_get_aligned_offset()
3062 (mt->tiling == I915_TILING_X || in use_intel_mipree_map_blit()
3248 case I915_TILING_X: in intel_miptree_get_isl_tiling()
Dintel_screen.c554 tiling = I915_TILING_X; in intel_create_image()
1213 uint32_t tiling = I915_TILING_X; in intel_detect_swizzling()
1954 uint32_t tiling = I915_TILING_X; in intelAllocateBuffer()
Dintel_tex_image.c517 (image->mt->tiling != I915_TILING_X && in intel_gettexsubimage_tiled_memcpy()
Dbrw_wm_surface_state.c272 case I915_TILING_X: in brw_get_surface_tiling_bits()
1664 if (mt->tiling == I915_TILING_X) { in update_texture_image_param()
Dintel_blit.c45 case I915_TILING_X: \
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_regions.c302 case I915_TILING_X: in intel_region_get_tile_masks()
344 case I915_TILING_X: in intel_region_get_aligned_offset()
Dintel_mipmap_tree.c157 return I915_TILING_X; in intel_miptree_choose_tiling()
193 bool y_or_x = tiling == (I915_TILING_Y | I915_TILING_X); in intel_miptree_create()
212 I915_TILING_X, in intel_miptree_create()
Dintel_screen.c438 tiling = I915_TILING_X; in intel_create_image()
1024 uint32_t tiling = I915_TILING_X; in intel_detect_swizzling()
1220 I915_TILING_X, in intelAllocateBuffer()
/external/libdrm/libkms/
Dintel.c127 tile.tiling_mode = I915_TILING_X; in intel_bo_create()
/external/mesa3d/src/intel/vulkan/
Danv_gem.c237 .stride = tiling == I915_TILING_X ? 512 : 128, in anv_gem_get_bit6_swizzle()
Danv_wsi.c210 surface->isl.row_pitch, I915_TILING_X); in x11_anv_wsi_image_create()
Danv_device.c171 bool swizzled = anv_gem_get_bit6_swizzle(fd, I915_TILING_X); in anv_physical_device_init()
/external/mesa3d/src/gallium/winsys/intel/drm/
Dintel_drm_winsys.c95 uint32_t tiling = I915_TILING_X, swizzle; in test_address_swizzling()
/external/kernel-headers/original/uapi/drm/
Di915_drm.h947 #define I915_TILING_X 1 macro
/external/libdrm/include/drm/
Di915_drm.h1011 #define I915_TILING_X 1 macro
/external/libdrm/intel/
Dintel_bufmgr_gem.c387 if (*tiling_mode == I915_TILING_X in drm_intel_gem_bo_tile_pitch()
929 else if (tiling == I915_TILING_X in drm_intel_gem_bo_alloc_tiled()