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Searched refs:IMPLICIT_DEF (Results 1 – 25 of 114) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Ddetect-dead-lanes.mir54 # undef operands or IMPLICIT_DEF definitions.
66 # CHECK: %3 = IMPLICIT_DEF
80 # CHECK: %8 = IMPLICIT_DEF
112 %3 = IMPLICIT_DEF
126 %8 = IMPLICIT_DEF
242 # CHECK: %1 = IMPLICIT_DEF
255 %1 = IMPLICIT_DEF
Di1-copy-implicit-def.ll4 ; SILowerI1Copies was not handling IMPLICIT_DEF
Drename-disconnected-bug.ll3 ; definition on every path (there should at least be IMPLICIT_DEF instructions).
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetOpcodes.h52 IMPLICIT_DEF = 8, enumerator
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dinsertelement-copytoregs.ll1 ; RUN: llc < %s -march=x86-64 | grep -v IMPLICIT_DEF
Dfp-stack-O0-crash.ll33 ; This produces a FP0 = IMPLICIT_DEF instruction.
D2008-01-16-InvalidDAGCombineXform.ll1 ; RUN: llc < %s -march=x86 | not grep IMPLICIT_DEF
/external/llvm/test/CodeGen/X86/
Dinsertelement-copytoregs.ll2 ; CHECK-NOT: IMPLICIT_DEF
Di16lshr8pat.ll12 ; CHECK-NOT: IMPLICIT_DEF
Dfp-stack-O0-crash.ll33 ; This produces a FP0 = IMPLICIT_DEF instruction.
Dcoalesce-implicitdef.ll11 ; This function creates an IMPLICIT_DEF with a long live range, even after
14 ; The coalescer should be able to deal with all kinds of IMPLICIT_DEF live
D2008-01-16-InvalidDAGCombineXform.ll1 ; RUN: llc < %s -march=x86 | not grep IMPLICIT_DEF
/external/llvm/test/CodeGen/PowerPC/
D2006-10-13-Miscompile.ll1 ; RUN: llc < %s -march=ppc32 | not grep IMPLICIT_DEF
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
D2006-10-13-Miscompile.ll1 ; RUN: llc < %s -march=ppc32 | not grep IMPLICIT_DEF
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1369 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1375 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1533 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1537 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1541 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1545 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1549 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1553 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1560 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
2810 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
[all …]
/external/llvm/lib/CodeGen/
DPatchableFunction.cpp46 case TargetOpcode::IMPLICIT_DEF: in doesNotGeneratecode()
DMachineSSAUpdater.cpp150 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
287 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
DProcessImplicitDefs.cpp90 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in processImplicitDef()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyPrepareForLiveIntervals.cpp118 TII.get(WebAssembly::IMPLICIT_DEF), Reg); in runOnMachineFunction()
/external/llvm/test/CodeGen/Generic/
Dundef-phi.ll4 ; inserts an IMPLICIT_DEF instruction in the predecessor so all paths to the use
/external/llvm/include/llvm/Target/
DTargetOpcodes.def51 /// defined by an IMPLICIT_DEF, because it is commonly used to implement
55 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
56 HANDLE_TARGET_OPCODE(IMPLICIT_DEF, 8)
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineSSAUpdater.cpp149 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
303 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
DProcessImplicitDefs.cpp153 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in runOnMachineFunction()
249 RMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in runOnMachineFunction()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp267 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
307 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
553 if (N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in initNumRegDefsLeft()
/external/llvm/lib/Target/AMDGPU/
DSILowerI1Copies.cpp84 if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) { in runOnMachineFunction()

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