| /external/llvm/test/CodeGen/AMDGPU/ |
| D | detect-dead-lanes.mir | 57 # CHECK: %1 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
58 # CHECK: %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, {{[0-9]+}}
67 # CHECK: %4 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
103 %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
104 %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, %subreg.sub0
113 %4 = INSERT_SUBREG %0, %3, %subreg.sub0
151 # CHECK: %9 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
156 # CHECK: %12 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
201 %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3
206 %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1
|
| D | insert_subreg.ll | 4 ; Test that INSERT_SUBREG instructions don't have non-register operands after
|
| /external/llvm/test/CodeGen/MIR/X86/ |
| D | subregister-index-operands.mir | 15 # CHECK: %0 = INSERT_SUBREG %edi, %al, {{[0-9]+}}
27 %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit
|
| D | unknown-subregister-index-op.mir | 24 %0 = INSERT_SUBREG %edi, %al, %subreg.bit8
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetOpcodes.h | 49 INSERT_SUBREG = 7, enumerator
|
| /external/llvm/lib/CodeGen/ |
| D | DetectDeadLanes.cpp | 147 case TargetOpcode::INSERT_SUBREG: in lowersToCopies()
170 case TargetOpcode::INSERT_SUBREG: in isCrossCopy()
248 case TargetOpcode::INSERT_SUBREG: { in transferUsedLanes()
324 case TargetOpcode::INSERT_SUBREG: { in transferDefinedLanes()
|
| D | ExpandPostRAPseudos.cpp | 219 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1369 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1375 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1533 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1537 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1541 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1545 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1549 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1553 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1560 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
2810 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
[all …]
|
| D | AArch64AdvSIMDScalarPass.cpp | 261 else if (Use->getOpcode() == AArch64::INSERT_SUBREG || in isProfitableToTransform()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetOpcodes.def | 47 /// INSERT_SUBREG - This instruction takes three operands: a register that
53 HANDLE_TARGET_OPCODE(INSERT_SUBREG, 7)
58 /// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
|
| /external/llvm/test/CodeGen/X86/ |
| D | i16lshr8pat.ll | 13 ; CHECK-NOT: INSERT_SUBREG
|
| D | crash-nosse.ll | 5 ; This test case produces INSERT_SUBREG 0, <undef> instructions that
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | crash-nosse.ll | 5 ; This test case produces INSERT_SUBREG 0, <undef> instructions that
|
| /external/llvm/lib/Target/X86/ |
| D | X86FixupSetCC.cpp | 173 TII->get(X86::INSERT_SUBREG), InsertReg) in runOnMachineFunction()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrFP.td | 102 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
392 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
399 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32),
405 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
412 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 229 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
| D | crash.ll | 27 ; The first INSERT_SUBREG needs an <undef> use operand for that to work.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 264 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
304 case TargetOpcode::INSERT_SUBREG: in reserveResources()
|
| D | ScheduleDAGRRList.cpp | 1896 Opc == TargetOpcode::INSERT_SUBREG) in getNodePriority()
2112 Opc == TargetOpcode::INSERT_SUBREG || in unscheduledNode()
2140 POpc == TargetOpcode::INSERT_SUBREG || in unscheduledNode()
2577 Opc == TargetOpcode::INSERT_SUBREG) in canEnableCoalescing()
2942 SuccOpc == TargetOpcode::INSERT_SUBREG || in AddPseudoTwoAddrDeps()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 54 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
106 case TargetOpcode::INSERT_SUBREG: in reserveResources()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 355 case AMDGPU::INSERT_SUBREG: { in runOnMachineFunction()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 806 return getOpcode() == TargetOpcode::INSERT_SUBREG;
849 case TargetOpcode::INSERT_SUBREG:
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineInstr.h | 276 return getOpcode() == TargetOpcode::INSERT_SUBREG;
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelDAGToDAG.cpp | 637 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT, in Select()
718 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl, ResVT, in Select()
|
| /external/llvm/test/CodeGen/Thumb2/ |
| D | crash.ll | 28 ; The first INSERT_SUBREG needs an <undef> use operand for that to work.
|