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Searched refs:INSERT_VECTOR_ELT (Results 1 – 25 of 39) sorted by relevance

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/external/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp339 if (ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
347 ISD == ISD::INSERT_VECTOR_ELT) in getVectorInstrCost()
DREADME_ALTIVEC.txt319 Currently EXTRACT_VECTOR_ELT and INSERT_VECTOR_ELT are type-legal only
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h258 INSERT_VECTOR_ELT, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h274 INSERT_VECTOR_ELT, enumerator
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp364 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
367 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
DLegalizeVectorTypes.cpp58 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
429 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
654 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
657 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
1238 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
1418 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, in WidenVecRes_Binary()
1872 return DAG.getNode(ISD::INSERT_VECTOR_ELT, N->getDebugLoc(), in WidenVecRes_INSERT_VECTOR_ELT()
2254 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
DLegalizeIntegerTypes.cpp83 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult()
766 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand()
2431 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand()
2978 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp171 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
172 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
173 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
174 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
199 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in R600TargetLowering()
618 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
910 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
1996 case ISD::INSERT_VECTOR_ELT: { in PerformDAGCombine()
DSIISelLowering.cpp147 case ISD::INSERT_VECTOR_ELT: in SITargetLowering()
171 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote); in SITargetLowering()
172 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32); in SITargetLowering()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp446 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Lo, Idx); in ExpandOp_INSERT_VECTOR_ELT()
450 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, NewVec, Hi, Idx); in ExpandOp_INSERT_VECTOR_ELT()
DLegalizeVectorTypes.cpp59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
602 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break; in SplitVectorResult()
989 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, in SplitVecRes_INSERT_VECTOR_ELT()
993 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt, in SplitVecRes_INSERT_VECTOR_ELT()
2064 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break; in WidenVectorResult()
2302 ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp, ConcatOps[OpIdx], in WidenVecRes_BinaryCanTrap()
2832 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), in WidenVecRes_INSERT_VECTOR_ELT()
3481 ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i], in BuildVectorFromScalar()
DSelectionDAGDumper.cpp218 case ISD::INSERT_VECTOR_ELT: return "insert_vector_elt"; in getOperationName()
DLegalizeIntegerTypes.cpp96 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerResult()
892 case ISD::INSERT_VECTOR_ELT: in PromoteIntegerOperand()
2753 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break; in ExpandIntegerOperand()
3388 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT, in PromoteIntRes_INSERT_VECTOR_ELT()
DLegalizeDAG.cpp2988 case ISD::INSERT_VECTOR_ELT: in ExpandNode()
4001 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) { in PromoteNode()
4316 case ISD::INSERT_VECTOR_ELT: { in PromoteNode()
4359 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT, in PromoteNode()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp701 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); in X86TargetLowering()
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in X86TargetLowering()
871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in X86TargetLowering()
875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); in X86TargetLowering()
941 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in X86TargetLowering()
942 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
943 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
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/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
626 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in ARMTargetLowering()
1490 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1504 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
3287 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
3290 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
5763 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT), in LowerBUILD_VECTOR()
5782 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops); in LowerBUILD_VECTOR()
5846 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
6423 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
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/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAIntType()
306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
1941 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2413 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, in lowerBUILD_VECTOR()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1954 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT, in HexagonTargetLowering()
1980 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom); in HexagonTargetLowering()
2678 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ? in LowerINSERT_VECTOR()
2772 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG); in LowerOperation()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetSelectionDAG.td361 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
460 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp306 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
386 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in SystemZTargetLowering()
387 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in SystemZTargetLowering()
4232 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I], in buildVector()
4346 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, in lowerSCALAR_TO_VECTOR()
4376 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT, in lowerINSERT_VECTOR_ELT()
4573 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
DSystemZISelDAGToDAG.cpp1311 case ISD::INSERT_VECTOR_ELT: { in Select()
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp495 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in AArch64TargetLowering()
666 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
2365 case ISD::INSERT_VECTOR_ELT: in LowerOperation()
5700 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec, in LowerVECTOR_SHUFFLE()
6387 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
6436 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
6447 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!"); in LowerINSERT_VECTOR_ELT()
6472 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, in LowerINSERT_VECTOR_ELT()
8700 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
8713 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT) in replaceSplatVectorStore()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); in ARMTargetLowering()
1136 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
1148 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, in LowerCallResult()
2530 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
2532 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, in LowerFormalArguments()
4479 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
4483 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, in LowerCONCAT_VECTORS()
7088 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, in PerformInsertEltCombine()
7940 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); in PerformDAGCombine()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td423 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
552 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp660 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); in X86TargetLowering()
767 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in X86TargetLowering()
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in X86TargetLowering()
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in X86TargetLowering()
813 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in X86TargetLowering()
1108 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
1302 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
1303 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom); in X86TargetLowering()
1396 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in X86TargetLowering()
[all …]

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