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1 #ifndef ISA_XML
2 #define ISA_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
9 
10 The rules-ng-ng source files this header was generated from are:
11 - isa.xml       (  24392 bytes, from 2016-11-16 18:54:37)
12 - copyright.xml (   1597 bytes, from 2016-10-02 14:26:13)
13 
14 Copyright (C) 2012-2016 by the following authors:
15 - Wladimir J. van der Laan <laanwj@gmail.com>
16 - Christian Gmeiner <christian.gmeiner@gmail.com>
17 - Lucas Stach <l.stach@pengutronix.de>
18 - Russell King <rmk@arm.linux.org.uk>
19 
20 Permission is hereby granted, free of charge, to any person obtaining a
21 copy of this software and associated documentation files (the "Software"),
22 to deal in the Software without restriction, including without limitation
23 the rights to use, copy, modify, merge, publish, distribute, sub license,
24 and/or sell copies of the Software, and to permit persons to whom the
25 Software is furnished to do so, subject to the following conditions:
26 
27 The above copyright notice and this permission notice (including the
28 next paragraph) shall be included in all copies or substantial portions
29 of the Software.
30 
31 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
32 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
33 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
34 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
35 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
36 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
37 DEALINGS IN THE SOFTWARE.
38 */
39 
40 
41 #define INST_OPCODE_NOP						0x00000000
42 #define INST_OPCODE_ADD						0x00000001
43 #define INST_OPCODE_MAD						0x00000002
44 #define INST_OPCODE_MUL						0x00000003
45 #define INST_OPCODE_DST						0x00000004
46 #define INST_OPCODE_DP3						0x00000005
47 #define INST_OPCODE_DP4						0x00000006
48 #define INST_OPCODE_DSX						0x00000007
49 #define INST_OPCODE_DSY						0x00000008
50 #define INST_OPCODE_MOV						0x00000009
51 #define INST_OPCODE_MOVAR					0x0000000a
52 #define INST_OPCODE_MOVAF					0x0000000b
53 #define INST_OPCODE_RCP						0x0000000c
54 #define INST_OPCODE_RSQ						0x0000000d
55 #define INST_OPCODE_LITP					0x0000000e
56 #define INST_OPCODE_SELECT					0x0000000f
57 #define INST_OPCODE_SET						0x00000010
58 #define INST_OPCODE_EXP						0x00000011
59 #define INST_OPCODE_LOG						0x00000012
60 #define INST_OPCODE_FRC						0x00000013
61 #define INST_OPCODE_CALL					0x00000014
62 #define INST_OPCODE_RET						0x00000015
63 #define INST_OPCODE_BRANCH					0x00000016
64 #define INST_OPCODE_TEXKILL					0x00000017
65 #define INST_OPCODE_TEXLD					0x00000018
66 #define INST_OPCODE_TEXLDB					0x00000019
67 #define INST_OPCODE_TEXLDD					0x0000001a
68 #define INST_OPCODE_TEXLDL					0x0000001b
69 #define INST_OPCODE_TEXLDPCF					0x0000001c
70 #define INST_OPCODE_REP						0x0000001d
71 #define INST_OPCODE_ENDREP					0x0000001e
72 #define INST_OPCODE_LOOP					0x0000001f
73 #define INST_OPCODE_ENDLOOP					0x00000020
74 #define INST_OPCODE_SQRT					0x00000021
75 #define INST_OPCODE_SIN						0x00000022
76 #define INST_OPCODE_COS						0x00000023
77 #define INST_OPCODE_FLOOR					0x00000025
78 #define INST_OPCODE_CEIL					0x00000026
79 #define INST_OPCODE_SIGN					0x00000027
80 #define INST_OPCODE_I2F						0x0000002d
81 #define INST_OPCODE_CMP						0x00000031
82 #define INST_OPCODE_LOAD					0x00000032
83 #define INST_OPCODE_STORE					0x00000033
84 #define INST_OPCODE_IMULLO0					0x0000003c
85 #define INST_OPCODE_IMULHI0					0x00000040
86 #define INST_OPCODE_IMADLO0					0x0000004c
87 #define INST_OPCODE_LEADZERO					0x00000058
88 #define INST_OPCODE_LSHIFT					0x00000059
89 #define INST_OPCODE_RSHIFT					0x0000005a
90 #define INST_OPCODE_ROTATE					0x0000005b
91 #define INST_OPCODE_OR						0x0000005c
92 #define INST_OPCODE_AND						0x0000005d
93 #define INST_OPCODE_XOR						0x0000005e
94 #define INST_OPCODE_NOT						0x0000005f
95 #define INST_CONDITION_TRUE					0x00000000
96 #define INST_CONDITION_GT					0x00000001
97 #define INST_CONDITION_LT					0x00000002
98 #define INST_CONDITION_GE					0x00000003
99 #define INST_CONDITION_LE					0x00000004
100 #define INST_CONDITION_EQ					0x00000005
101 #define INST_CONDITION_NE					0x00000006
102 #define INST_CONDITION_AND					0x00000007
103 #define INST_CONDITION_OR					0x00000008
104 #define INST_CONDITION_XOR					0x00000009
105 #define INST_CONDITION_NOT					0x0000000a
106 #define INST_CONDITION_NZ					0x0000000b
107 #define INST_CONDITION_GEZ					0x0000000c
108 #define INST_CONDITION_GZ					0x0000000d
109 #define INST_CONDITION_LEZ					0x0000000e
110 #define INST_CONDITION_LZ					0x0000000f
111 #define INST_RGROUP_TEMP					0x00000000
112 #define INST_RGROUP_INTERNAL					0x00000001
113 #define INST_RGROUP_UNIFORM_0					0x00000002
114 #define INST_RGROUP_UNIFORM_1					0x00000003
115 #define INST_AMODE_DIRECT					0x00000000
116 #define INST_AMODE_ADD_A_X					0x00000001
117 #define INST_AMODE_ADD_A_Y					0x00000002
118 #define INST_AMODE_ADD_A_Z					0x00000003
119 #define INST_AMODE_ADD_A_W					0x00000004
120 #define INST_SWIZ_COMP_X					0x00000000
121 #define INST_SWIZ_COMP_Y					0x00000001
122 #define INST_SWIZ_COMP_Z					0x00000002
123 #define INST_SWIZ_COMP_W					0x00000003
124 #define INST_TYPE_F32						0x00000000
125 #define INST_TYPE_S32						0x00000001
126 #define INST_TYPE_S8						0x00000002
127 #define INST_TYPE_U16						0x00000003
128 #define INST_TYPE_F16						0x00000004
129 #define INST_TYPE_S16						0x00000005
130 #define INST_TYPE_U32						0x00000006
131 #define INST_TYPE_U8						0x00000007
132 #define INST_COMPS_X						0x00000001
133 #define INST_COMPS_Y						0x00000002
134 #define INST_COMPS_Z						0x00000004
135 #define INST_COMPS_W						0x00000008
136 #define INST_SWIZ_X__MASK					0x00000003
137 #define INST_SWIZ_X__SHIFT					0
138 #define INST_SWIZ_X(x)						(((x) << INST_SWIZ_X__SHIFT) & INST_SWIZ_X__MASK)
139 #define INST_SWIZ_Y__MASK					0x0000000c
140 #define INST_SWIZ_Y__SHIFT					2
141 #define INST_SWIZ_Y(x)						(((x) << INST_SWIZ_Y__SHIFT) & INST_SWIZ_Y__MASK)
142 #define INST_SWIZ_Z__MASK					0x00000030
143 #define INST_SWIZ_Z__SHIFT					4
144 #define INST_SWIZ_Z(x)						(((x) << INST_SWIZ_Z__SHIFT) & INST_SWIZ_Z__MASK)
145 #define INST_SWIZ_W__MASK					0x000000c0
146 #define INST_SWIZ_W__SHIFT					6
147 #define INST_SWIZ_W(x)						(((x) << INST_SWIZ_W__SHIFT) & INST_SWIZ_W__MASK)
148 #define VIV_ISA_WORD_0						0x00000000
149 #define VIV_ISA_WORD_0_OPCODE__MASK				0x0000003f
150 #define VIV_ISA_WORD_0_OPCODE__SHIFT				0
151 #define VIV_ISA_WORD_0_OPCODE(x)				(((x) << VIV_ISA_WORD_0_OPCODE__SHIFT) & VIV_ISA_WORD_0_OPCODE__MASK)
152 #define VIV_ISA_WORD_0_COND__MASK				0x000007c0
153 #define VIV_ISA_WORD_0_COND__SHIFT				6
154 #define VIV_ISA_WORD_0_COND(x)					(((x) << VIV_ISA_WORD_0_COND__SHIFT) & VIV_ISA_WORD_0_COND__MASK)
155 #define VIV_ISA_WORD_0_SAT					0x00000800
156 #define VIV_ISA_WORD_0_DST_USE					0x00001000
157 #define VIV_ISA_WORD_0_DST_AMODE__MASK				0x0000e000
158 #define VIV_ISA_WORD_0_DST_AMODE__SHIFT				13
159 #define VIV_ISA_WORD_0_DST_AMODE(x)				(((x) << VIV_ISA_WORD_0_DST_AMODE__SHIFT) & VIV_ISA_WORD_0_DST_AMODE__MASK)
160 #define VIV_ISA_WORD_0_DST_REG__MASK				0x007f0000
161 #define VIV_ISA_WORD_0_DST_REG__SHIFT				16
162 #define VIV_ISA_WORD_0_DST_REG(x)				(((x) << VIV_ISA_WORD_0_DST_REG__SHIFT) & VIV_ISA_WORD_0_DST_REG__MASK)
163 #define VIV_ISA_WORD_0_DST_COMPS__MASK				0x07800000
164 #define VIV_ISA_WORD_0_DST_COMPS__SHIFT				23
165 #define VIV_ISA_WORD_0_DST_COMPS(x)				(((x) << VIV_ISA_WORD_0_DST_COMPS__SHIFT) & VIV_ISA_WORD_0_DST_COMPS__MASK)
166 #define VIV_ISA_WORD_0_TEX_ID__MASK				0xf8000000
167 #define VIV_ISA_WORD_0_TEX_ID__SHIFT				27
168 #define VIV_ISA_WORD_0_TEX_ID(x)				(((x) << VIV_ISA_WORD_0_TEX_ID__SHIFT) & VIV_ISA_WORD_0_TEX_ID__MASK)
169 
170 #define VIV_ISA_WORD_1						0x00000004
171 #define VIV_ISA_WORD_1_TEX_AMODE__MASK				0x00000007
172 #define VIV_ISA_WORD_1_TEX_AMODE__SHIFT				0
173 #define VIV_ISA_WORD_1_TEX_AMODE(x)				(((x) << VIV_ISA_WORD_1_TEX_AMODE__SHIFT) & VIV_ISA_WORD_1_TEX_AMODE__MASK)
174 #define VIV_ISA_WORD_1_TEX_SWIZ__MASK				0x000007f8
175 #define VIV_ISA_WORD_1_TEX_SWIZ__SHIFT				3
176 #define VIV_ISA_WORD_1_TEX_SWIZ(x)				(((x) << VIV_ISA_WORD_1_TEX_SWIZ__SHIFT) & VIV_ISA_WORD_1_TEX_SWIZ__MASK)
177 #define VIV_ISA_WORD_1_SRC0_USE					0x00000800
178 #define VIV_ISA_WORD_1_SRC0_REG__MASK				0x001ff000
179 #define VIV_ISA_WORD_1_SRC0_REG__SHIFT				12
180 #define VIV_ISA_WORD_1_SRC0_REG(x)				(((x) << VIV_ISA_WORD_1_SRC0_REG__SHIFT) & VIV_ISA_WORD_1_SRC0_REG__MASK)
181 #define VIV_ISA_WORD_1_TYPE_BIT2				0x00200000
182 #define VIV_ISA_WORD_1_SRC0_SWIZ__MASK				0x3fc00000
183 #define VIV_ISA_WORD_1_SRC0_SWIZ__SHIFT				22
184 #define VIV_ISA_WORD_1_SRC0_SWIZ(x)				(((x) << VIV_ISA_WORD_1_SRC0_SWIZ__SHIFT) & VIV_ISA_WORD_1_SRC0_SWIZ__MASK)
185 #define VIV_ISA_WORD_1_SRC0_NEG					0x40000000
186 #define VIV_ISA_WORD_1_SRC0_ABS					0x80000000
187 
188 #define VIV_ISA_WORD_2						0x00000008
189 #define VIV_ISA_WORD_2_SRC0_AMODE__MASK				0x00000007
190 #define VIV_ISA_WORD_2_SRC0_AMODE__SHIFT			0
191 #define VIV_ISA_WORD_2_SRC0_AMODE(x)				(((x) << VIV_ISA_WORD_2_SRC0_AMODE__SHIFT) & VIV_ISA_WORD_2_SRC0_AMODE__MASK)
192 #define VIV_ISA_WORD_2_SRC0_RGROUP__MASK			0x00000038
193 #define VIV_ISA_WORD_2_SRC0_RGROUP__SHIFT			3
194 #define VIV_ISA_WORD_2_SRC0_RGROUP(x)				(((x) << VIV_ISA_WORD_2_SRC0_RGROUP__SHIFT) & VIV_ISA_WORD_2_SRC0_RGROUP__MASK)
195 #define VIV_ISA_WORD_2_SRC1_USE					0x00000040
196 #define VIV_ISA_WORD_2_SRC1_REG__MASK				0x0000ff80
197 #define VIV_ISA_WORD_2_SRC1_REG__SHIFT				7
198 #define VIV_ISA_WORD_2_SRC1_REG(x)				(((x) << VIV_ISA_WORD_2_SRC1_REG__SHIFT) & VIV_ISA_WORD_2_SRC1_REG__MASK)
199 #define VIV_ISA_WORD_2_OPCODE_BIT6				0x00010000
200 #define VIV_ISA_WORD_2_SRC1_SWIZ__MASK				0x01fe0000
201 #define VIV_ISA_WORD_2_SRC1_SWIZ__SHIFT				17
202 #define VIV_ISA_WORD_2_SRC1_SWIZ(x)				(((x) << VIV_ISA_WORD_2_SRC1_SWIZ__SHIFT) & VIV_ISA_WORD_2_SRC1_SWIZ__MASK)
203 #define VIV_ISA_WORD_2_SRC1_NEG					0x02000000
204 #define VIV_ISA_WORD_2_SRC1_ABS					0x04000000
205 #define VIV_ISA_WORD_2_SRC1_AMODE__MASK				0x38000000
206 #define VIV_ISA_WORD_2_SRC1_AMODE__SHIFT			27
207 #define VIV_ISA_WORD_2_SRC1_AMODE(x)				(((x) << VIV_ISA_WORD_2_SRC1_AMODE__SHIFT) & VIV_ISA_WORD_2_SRC1_AMODE__MASK)
208 #define VIV_ISA_WORD_2_TYPE_BIT01__MASK				0xc0000000
209 #define VIV_ISA_WORD_2_TYPE_BIT01__SHIFT			30
210 #define VIV_ISA_WORD_2_TYPE_BIT01(x)				(((x) << VIV_ISA_WORD_2_TYPE_BIT01__SHIFT) & VIV_ISA_WORD_2_TYPE_BIT01__MASK)
211 
212 #define VIV_ISA_WORD_3						0x0000000c
213 #define VIV_ISA_WORD_3_SRC1_RGROUP__MASK			0x00000007
214 #define VIV_ISA_WORD_3_SRC1_RGROUP__SHIFT			0
215 #define VIV_ISA_WORD_3_SRC1_RGROUP(x)				(((x) << VIV_ISA_WORD_3_SRC1_RGROUP__SHIFT) & VIV_ISA_WORD_3_SRC1_RGROUP__MASK)
216 #define VIV_ISA_WORD_3_SRC2_IMM__MASK				0x003fff80
217 #define VIV_ISA_WORD_3_SRC2_IMM__SHIFT				7
218 #define VIV_ISA_WORD_3_SRC2_IMM(x)				(((x) << VIV_ISA_WORD_3_SRC2_IMM__SHIFT) & VIV_ISA_WORD_3_SRC2_IMM__MASK)
219 #define VIV_ISA_WORD_3_SRC2_USE					0x00000008
220 #define VIV_ISA_WORD_3_SRC2_REG__MASK				0x00001ff0
221 #define VIV_ISA_WORD_3_SRC2_REG__SHIFT				4
222 #define VIV_ISA_WORD_3_SRC2_REG(x)				(((x) << VIV_ISA_WORD_3_SRC2_REG__SHIFT) & VIV_ISA_WORD_3_SRC2_REG__MASK)
223 #define VIV_ISA_WORD_3_UNK3_13					0x00002000
224 #define VIV_ISA_WORD_3_SRC2_SWIZ__MASK				0x003fc000
225 #define VIV_ISA_WORD_3_SRC2_SWIZ__SHIFT				14
226 #define VIV_ISA_WORD_3_SRC2_SWIZ(x)				(((x) << VIV_ISA_WORD_3_SRC2_SWIZ__SHIFT) & VIV_ISA_WORD_3_SRC2_SWIZ__MASK)
227 #define VIV_ISA_WORD_3_SRC2_NEG					0x00400000
228 #define VIV_ISA_WORD_3_SRC2_ABS					0x00800000
229 #define VIV_ISA_WORD_3_UNK3_24					0x01000000
230 #define VIV_ISA_WORD_3_SRC2_AMODE__MASK				0x0e000000
231 #define VIV_ISA_WORD_3_SRC2_AMODE__SHIFT			25
232 #define VIV_ISA_WORD_3_SRC2_AMODE(x)				(((x) << VIV_ISA_WORD_3_SRC2_AMODE__SHIFT) & VIV_ISA_WORD_3_SRC2_AMODE__MASK)
233 #define VIV_ISA_WORD_3_SRC2_RGROUP__MASK			0x70000000
234 #define VIV_ISA_WORD_3_SRC2_RGROUP__SHIFT			28
235 #define VIV_ISA_WORD_3_SRC2_RGROUP(x)				(((x) << VIV_ISA_WORD_3_SRC2_RGROUP__SHIFT) & VIV_ISA_WORD_3_SRC2_RGROUP__MASK)
236 #define VIV_ISA_WORD_3_UNK3_31					0x80000000
237 
238 
239 #endif /* ISA_XML */
240