| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 156 INTRINSIC_VOID, enumerator
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| D | SelectionDAGNodes.h | 1087 N->getOpcode() == ISD::INTRINSIC_VOID ||
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 161 INTRINSIC_VOID, enumerator
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| D | SelectionDAGNodes.h | 484 NodeType == ISD::INTRINSIC_VOID) && ((SubclassData >> 13) & 1);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 117 case ISD::INTRINSIC_VOID: in getOperationName()
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| D | TargetLowering.cpp | 1187 Op.getOpcode() == ISD::INTRINSIC_VOID) && in computeKnownBitsForTargetNode()
1201 Op.getOpcode() == ISD::INTRINSIC_VOID) && in ComputeNumSignBitsForTargetNode()
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| D | SelectionDAG.cpp | 2489 case ISD::INTRINSIC_VOID: in computeKnownBits()
2748 Op.getOpcode() == ISD::INTRINSIC_VOID) { in ComputeNumSignBits()
4980 assert((Opcode == ISD::INTRINSIC_VOID || in getMemIntrinsicNode()
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| D | LegalizeDAG.cpp | 949 case ISD::INTRINSIC_VOID: in LegalizeOp()
3726 case ISD::INTRINSIC_VOID: in ExpandNode()
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| D | SelectionDAGISel.cpp | 3574 N->getOpcode() != ISD::INTRINSIC_VOID) { in CannotYetSelect()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 847 case ISD::INTRINSIC_VOID: { in trySelect()
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| D | MipsSEISelLowering.cpp | 148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in MipsSETargetLowering()
375 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 175 setTargetDAGCombine(ISD::INTRINSIC_VOID); in XCoreTargetLowering()
1608 case ISD::INTRINSIC_VOID: in PerformDAGCombine()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 869 setTargetDAGCombine(ISD::INTRINSIC_VOID); in PPCTargetLowering()
7929 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, in LowerEXTRACT_VECTOR_ELT()
8135 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, in LowerVectorStore()
9625 if (N->getOpcode() == ISD::INTRINSIC_VOID) { in isConsecutiveLS()
10518 case ISD::INTRINSIC_VOID: { in expandVSXStoreForLE()
10978 case ISD::INTRINSIC_VOID: { in PerformDAGCombine()
11825 Info.opc = ISD::INTRINSIC_VOID; in getTgtMemIntrinsic()
11860 Info.opc = ISD::INTRINSIC_VOID; in getTgtMemIntrinsic()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 2081 case ISD::INTRINSIC_VOID: in ComputeMaskedBits()
2281 Op.getOpcode() == ISD::INTRINSIC_VOID) { in ComputeNumSignBits()
4073 assert((Opcode == ISD::INTRINSIC_VOID || in getMemIntrinsicNode()
5924 case ISD::INTRINSIC_VOID: in getOperationName()
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| D | TargetLowering.cpp | 1851 Op.getOpcode() == ISD::INTRINSIC_VOID) && in computeMaskedBitsForTargetNode()
1865 Op.getOpcode() == ISD::INTRINSIC_VOID) && in ComputeNumSignBitsForTargetNode()
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| D | SelectionDAGISel.cpp | 2806 N->getOpcode() != ISD::INTRINSIC_VOID) { in CannotYetSelect()
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| D | LegalizeDAG.cpp | 800 case ISD::INTRINSIC_VOID: in LegalizeOp()
3818 case ISD::INTRINSIC_VOID: in ExpandNode()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1255 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
1402 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL, in LowerBRCOND()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1799 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in HexagonTargetLowering()
2799 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 475 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 569 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1143 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores in SelectAddr()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 505 setTargetDAGCombine(ISD::INTRINSIC_VOID); in ARMTargetLowering()
7154 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || in CombineBaseUpdate()
7959 case ISD::INTRINSIC_VOID: in PerformDAGCombine()
8791 Info.opc = ISD::INTRINSIC_VOID; in getTgtMemIntrinsic()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1474 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores in selectAddr()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 615 setTargetDAGCombine(ISD::INTRINSIC_VOID); in ARMTargetLowering()
3027 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0), in LowerATOMIC_FENCE()
9898 const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || in CombineBaseUpdate()
11070 case ISD::INTRINSIC_VOID: in PerformDAGCombine()
12234 Info.opc = ISD::INTRINSIC_VOID; in getTgtMemIntrinsic()
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