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Searched refs:Imm (Results 1 – 25 of 293) sorted by relevance

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/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64AddressingModes.h73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) { in getShiftType() argument
74 switch ((Imm >> 6) & 0x7) { in getShiftType()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() argument
86 return Imm & 0x3f; in getShiftValue()
99 unsigned Imm) { in getShifterImm() argument
100 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!"); in getShifterImm()
110 return (STEnc << 6) | (Imm & 0x3f); in getShifterImm()
118 static inline unsigned getArithShiftValue(unsigned Imm) { in getArithShiftValue() argument
119 return Imm & 0x7; in getArithShiftValue()
123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) { in getExtendType() argument
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h111 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
112 return ShOp | (Imm << 3); in getSORegOpc()
123 static inline unsigned getSOImmValImm(unsigned Imm) { in getSOImmValImm() argument
124 return Imm & 0xFF; in getSOImmValImm()
128 static inline unsigned getSOImmValRot(unsigned Imm) { in getSOImmValRot() argument
129 return (Imm >> 8) * 2; in getSOImmValRot()
136 static inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
139 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
142 unsigned TZ = CountTrailingZeros_32(Imm); in getSOImmValRotate()
149 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
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/external/llvm/lib/Target/SystemZ/
DSystemZTargetTransformInfo.cpp34 int SystemZTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
46 if (Imm == 0) in getIntImmCost()
49 if (Imm.getBitWidth() <= 64) { in getIntImmCost()
51 if (isInt<32>(Imm.getSExtValue())) in getIntImmCost()
54 if (isUInt<32>(Imm.getZExtValue())) in getIntImmCost()
57 if ((Imm.getZExtValue() & 0xffffffff) == 0) in getIntImmCost()
67 const APInt &Imm, Type *Ty) { in getIntImmCost() argument
90 if (Idx == 0 && Imm.getBitWidth() <= 64) { in getIntImmCost()
95 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
100 if (Idx == 1 && Imm.getBitWidth() <= 64) { in getIntImmCost()
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/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc() argument
113 return ShOp | (Imm << 3); in getSORegOpc()
124 static inline unsigned getSOImmValImm(unsigned Imm) { in getSOImmValImm() argument
125 return Imm & 0xFF; in getSOImmValImm()
129 static inline unsigned getSOImmValRot(unsigned Imm) { in getSOImmValRot() argument
130 return (Imm >> 8) * 2; in getSOImmValRot()
137 static inline unsigned getSOImmValRotate(unsigned Imm) { in getSOImmValRotate() argument
140 if ((Imm & ~255U) == 0) return 0; in getSOImmValRotate()
143 unsigned TZ = countTrailingZeros(Imm); in getSOImmValRotate()
150 if ((rotr32(Imm, RotAmt) & ~255U) == 0) in getSOImmValRotate()
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/external/llvm/lib/Target/Mips/
DMipsAnalyzeImmediate.cpp29 void MipsAnalyzeImmediate::GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, in GetInstSeqLsADDiu() argument
31 GetInstSeqLs((Imm + 0x8000ULL) & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsADDiu()
32 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
35 void MipsAnalyzeImmediate::GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, in GetInstSeqLsORi() argument
37 GetInstSeqLs(Imm & 0xffffffffffff0000ULL, RemSize, SeqLs); in GetInstSeqLsORi()
38 AddInstr(SeqLs, Inst(ORi, Imm & 0xffffULL)); in GetInstSeqLsORi()
41 void MipsAnalyzeImmediate::GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, in GetInstSeqLsSLL() argument
43 unsigned Shamt = countTrailingZeros(Imm); in GetInstSeqLsSLL()
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs); in GetInstSeqLsSLL()
48 void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, in GetInstSeqLs() argument
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DMipsISelDAGToDAG.h88 virtual bool selectVSplat(SDNode *N, APInt &Imm,
91 virtual bool selectVSplatUimm1(SDValue N, SDValue &Imm) const;
93 virtual bool selectVSplatUimm2(SDValue N, SDValue &Imm) const;
95 virtual bool selectVSplatUimm3(SDValue N, SDValue &Imm) const;
97 virtual bool selectVSplatUimm4(SDValue N, SDValue &Imm) const;
99 virtual bool selectVSplatUimm5(SDValue N, SDValue &Imm) const;
101 virtual bool selectVSplatUimm6(SDValue N, SDValue &Imm) const;
103 virtual bool selectVSplatUimm8(SDValue N, SDValue &Imm) const;
105 virtual bool selectVSplatSimm5(SDValue N, SDValue &Imm) const;
107 virtual bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const;
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DMipsSEISelDAGToDAG.h89 bool selectVSplat(SDNode *N, APInt &Imm,
92 bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
95 bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
97 bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
99 bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
101 bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
103 bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
105 bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
107 bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
109 bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
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DMipsISelDAGToDAG.cpp129 bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm, in selectVSplat() argument
135 bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const { in selectVSplatUimm1()
140 bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const { in selectVSplatUimm2()
145 bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const { in selectVSplatUimm3()
150 bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const { in selectVSplatUimm4()
155 bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const { in selectVSplatUimm5()
160 bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const { in selectVSplatUimm6()
165 bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const { in selectVSplatUimm8()
170 bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const { in selectVSplatSimm5()
175 bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const { in selectVSplatUimmPow2()
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DMipsAnalyzeImmediate.h28 const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu);
37 void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
41 void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
45 void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
48 void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs);
/external/llvm/test/MC/Lanai/
Dmemory.s12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
28 ! CHECK-NEXT: <MCOperand Imm:0>
29 ! CHECK-NEXT: <MCOperand Imm:0>
36 ! CHECK-NEXT: <MCOperand Imm:291>
37 ! CHECK-NEXT: <MCOperand Imm:128>
44 ! CHECK-NEXT: <MCOperand Imm:-4>
45 ! CHECK-NEXT: <MCOperand Imm:128>
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Dconditional_inst.s16 ! CHECK-NEXT: <MCOperand Imm:4660>
22 ! CHECK-NEXT: <MCOperand Imm:2000>
23 ! CHECK-NEXT: <MCOperand Imm:13>
31 ! CHECK-NEXT: <MCOperand Imm:13>
38 ! CHECK-NEXT: <MCOperand Imm:10>
53 ! CHECK-NEXT: <MCOperand Imm:10>
59 ! CHECK-NEXT: <MCOperand Imm:1110>
60 ! CHECK-NEXT: <MCOperand Imm:1>
69 ! CHECK-NEXT: <MCOperand Imm:12>>
77 ! CHECK-NEXT: <MCOperand Imm:0>>
/external/swiftshader/third_party/LLVM/lib/Target/X86/Utils/
DX86ShuffleDecode.cpp23 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask) { in DecodeINSERTPSMask() argument
31 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
32 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
33 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask()
66 void DecodePSHUFMask(unsigned NElts, unsigned Imm, in DecodePSHUFMask() argument
69 ShuffleMask.push_back(Imm % NElts); in DecodePSHUFMask()
70 Imm /= NElts; in DecodePSHUFMask()
74 void DecodePSHUFHWMask(unsigned Imm, in DecodePSHUFHWMask() argument
81 ShuffleMask.push_back(4+(Imm & 3)); in DecodePSHUFHWMask()
82 Imm >>= 2; in DecodePSHUFHWMask()
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DX86ShuffleDecode.h30 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<unsigned> &ShuffleMask);
40 void DecodePSHUFMask(unsigned NElts, unsigned Imm,
43 void DecodePSHUFHWMask(unsigned Imm,
46 void DecodePSHUFLWMask(unsigned Imm,
67 void DecodeSHUFPSMask(unsigned NElts, unsigned Imm,
90 void DecodeVPERMILPSMask(unsigned NElts, unsigned Imm,
97 void DecodeVPERMILPDMask(unsigned NElts, unsigned Imm,
100 void DecodeVPERM2F128Mask(unsigned Imm,
102 void DecodeVPERM2F128Mask(EVT VT, unsigned Imm,
/external/llvm/lib/Target/AMDGPU/InstPrinter/
DAMDGPUInstPrinter.cpp101 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset() local
102 if (Imm != 0) { in printOffset()
307 void AMDGPUInstPrinter::printImmediate32(uint32_t Imm, raw_ostream &O) { in printImmediate32() argument
308 int32_t SImm = static_cast<int32_t>(Imm); in printImmediate32()
314 if (Imm == FloatToBits(0.0f)) in printImmediate32()
316 else if (Imm == FloatToBits(1.0f)) in printImmediate32()
318 else if (Imm == FloatToBits(-1.0f)) in printImmediate32()
320 else if (Imm == FloatToBits(0.5f)) in printImmediate32()
322 else if (Imm == FloatToBits(-0.5f)) in printImmediate32()
324 else if (Imm == FloatToBits(2.0f)) in printImmediate32()
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/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp154 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm) { in decodeUImmOperand() argument
155 if (!isUInt<N>(Imm)) in decodeUImmOperand()
157 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
162 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm) { in decodeSImmOperand() argument
163 if (!isUInt<N>(Imm)) in decodeSImmOperand()
165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
169 static DecodeStatus decodeAccessRegOperand(MCInst &Inst, uint64_t Imm, in decodeAccessRegOperand() argument
172 return decodeUImmOperand<4>(Inst, Imm); in decodeAccessRegOperand()
175 static DecodeStatus decodeU1ImmOperand(MCInst &Inst, uint64_t Imm, in decodeU1ImmOperand() argument
177 return decodeUImmOperand<1>(Inst, Imm); in decodeU1ImmOperand()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonInstPrinter.cpp130 int64_t Imm; in prints3_6ImmOperand() local
131 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); in prints3_6ImmOperand()
132 Imm = SignExtend64<9>(Imm); in prints3_6ImmOperand()
134 assert(((Imm & 0x3f) == 0) && "Lower 6 bits must be ZERO."); in prints3_6ImmOperand()
135 O << formatImm(Imm/64); in prints3_6ImmOperand()
140 int64_t Imm; in prints3_7ImmOperand() local
141 bool Success = MI->getOperand(OpNo).getExpr()->evaluateAsAbsolute(Imm); in prints3_7ImmOperand()
142 Imm = SignExtend64<10>(Imm); in prints3_7ImmOperand()
144 assert(((Imm & 0x7f) == 0) && "Lower 7 bits must be ZERO."); in prints3_7ImmOperand()
145 O << formatImm(Imm/128); in prints3_7ImmOperand()
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/external/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp45 int PPCTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) { in getIntImmCost() argument
47 return BaseT::getIntImmCost(Imm, Ty); in getIntImmCost()
55 if (Imm == 0) in getIntImmCost()
58 if (Imm.getBitWidth() <= 64) { in getIntImmCost()
59 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
62 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
64 if ((Imm.getZExtValue() & 0xFFFF) == 0) in getIntImmCost()
74 int PPCTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, in getIntImmCost() argument
77 return BaseT::getIntImmCost(IID, Idx, Imm, Ty); in getIntImmCost()
92 if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<16>(Imm.getSExtValue())) in getIntImmCost()
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp63 inline SDValue getI32Imm(unsigned Imm) { in getI32Imm() argument
64 return CurDAG->getTargetConstant(Imm, MVT::i32); in getI32Imm()
69 inline SDValue getI64Imm(uint64_t Imm) { in getI64Imm() argument
70 return CurDAG->getTargetConstant(Imm, MVT::i64); in getI64Imm()
74 inline SDValue getSmallIPtrImm(unsigned Imm) { in getSmallIPtrImm() argument
75 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); in getSmallIPtrImm()
259 static bool isIntS16Immediate(SDNode *N, short &Imm) { in isIntS16Immediate() argument
263 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
265 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
267 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); in isIntS16Immediate()
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/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.h31 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
54 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
56 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
61 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
66 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
71 void DecodePSHUFLWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
79 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
101 void DecodeBLENDMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
103 void DecodeVPERM2X128Mask(MVT VT, unsigned Imm,
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DX86ShuffleDecode.cpp25 void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeINSERTPSMask() argument
33 unsigned ZMask = Imm & 15; in DecodeINSERTPSMask()
34 unsigned CountD = (Imm >> 4) & 3; in DecodeINSERTPSMask()
35 unsigned CountS = (Imm >> 6) & 3; in DecodeINSERTPSMask()
107 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask() argument
116 if (i >= Imm) M = i - Imm + l; in DecodePSLLDQMask()
121 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSRLDQMask() argument
129 unsigned Base = i + Imm; in DecodePSRLDQMask()
136 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask() argument
139 unsigned Offset = Imm * (VT.getVectorElementType().getSizeInBits() / 8); in DecodePALIGNRMask()
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/external/llvm/lib/Target/X86/InstPrinter/
DX86ATTInstPrinter.cpp74 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC() local
75 switch (Imm) { in printSSEAVXCC()
114 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC() local
115 switch (Imm) { in printXOPCC()
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl() local
131 switch (Imm) { in printRoundingControl()
169 int64_t Imm = Op.getImm(); in printOperand() local
170 O << markup("<imm:") << '$' << formatImm(Imm) << markup(">"); in printOperand()
178 if (CommentStream && !HasCustomInstComment && (Imm > 255 || Imm < -256)) { in printOperand()
180 if (Imm == (int16_t)(Imm)) in printOperand()
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp89 static uint32_t getIntInlineImmEncoding(IntTy Imm) { in getIntInlineImmEncoding() argument
90 if (Imm >= 0 && Imm <= 64) in getIntInlineImmEncoding()
91 return 128 + Imm; in getIntInlineImmEncoding()
93 if (Imm >= -16 && Imm <= -1) in getIntInlineImmEncoding()
94 return 192 + std::abs(Imm); in getIntInlineImmEncoding()
166 int64_t Imm; in getLitEncoding() local
172 Imm = C->getValue(); in getLitEncoding()
180 Imm = MO.getImm(); in getLitEncoding()
184 return getLit32Encoding(static_cast<uint32_t>(Imm)); in getLitEncoding()
188 return getLit64Encoding(static_cast<uint64_t>(Imm)); in getLitEncoding()
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/external/llvm/lib/Target/NVPTX/InstPrinter/
DNVPTXInstPrinter.cpp95 int64_t Imm = MO.getImm(); in printCvtMode() local
99 if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG) in printCvtMode()
103 if (Imm & NVPTX::PTXCvtMode::SAT_FLAG) in printCvtMode()
107 switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) { in printCvtMode()
145 int64_t Imm = MO.getImm(); in printCmpMode() local
149 if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG) in printCmpMode()
152 switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) { in printCmpMode()
219 int Imm = (int) MO.getImm(); in printLdStCode() local
221 if (Imm) in printLdStCode()
224 switch (Imm) { in printLdStCode()
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/external/swiftshader/third_party/subzero/unittest/AssemblerX8632/
DDataMov.cpp177 #define TestMovzx8bitWithRegDest(Src, Dst, Imm) \ in TEST_F() argument
179 static_assert(((Imm)&0xFF) == (Imm), #Imm " is not an 8bit immediate"); \ in TEST_F()
180 __ mov(IceType_i8, GPRRegister::Encoded_Reg_##Src, Immediate(Imm)); \ in TEST_F()
185 ASSERT_EQ(Imm, test.Dst()) << "(" #Src ", " #Dst ", " #Imm ")"; \ in TEST_F()
189 #define TestMovzx16bitWithRegDest(Src, Dst, Imm) \ in TEST_F() argument
191 static_assert(((Imm)&0xFFFF) == (Imm), #Imm " is not a 16bit immediate"); \ in TEST_F()
192 __ mov(IceType_i16, GPRRegister::Encoded_Reg_##Src, Immediate(Imm)); \ in TEST_F()
197 ASSERT_EQ(Imm, test.Dst()) << "(" #Src ", " #Dst ", " #Imm ")"; \ in TEST_F()
201 #define TestMovzx8bitWithAddrSrc(Dst, Imm) \ in TEST_F() argument
203 static_assert(((Imm)&0xFF) == (Imm), #Imm " is not an 8bit immediate"); \ in TEST_F()
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/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp191 MCStreamer &OutStreamer, const MCOperand &Imm, in smallData() argument
195 if (Imm.getExpr()->evaluateAsAbsolute(Value)) { in smallData()
225 assert(Imm.isExpr() && "Expected expression and found none"); in smallData()
249 OutStreamer.EmitValue(Imm.getExpr(), AlignSize); in smallData()
281 const MCOperand &Imm = MappedInst.getOperand(1); in HexagonProcessInstruction() local
284 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8); in HexagonProcessInstruction()
302 MCOperand &Imm = MappedInst.getOperand(1); in HexagonProcessInstruction() local
304 MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4); in HexagonProcessInstruction()
377 int64_t Imm; in HexagonProcessInstruction() local
379 bool Success = Expr->evaluateAsAbsolute(Imm); in HexagonProcessInstruction()
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