| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 249 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
253 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
257 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
261 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in emitPrologue()
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| D | SIRegisterInfo.cpp | 601 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in eliminateFrameIndex()
624 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine); in eliminateFrameIndex()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 217 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in convertToBRCT()
231 .addReg(SystemZ::CC, RegState::ImplicitDefine); in convertToLoadAndTest()
449 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in fuseCompareOperations()
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| D | SystemZShortenInst.cpp | 147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead); in shortenOn001AddCC()
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| D | SystemZFrameLowering.cpp | 269 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinRegisterInfo.cpp | 146 .addReg(Reg, RegState::ImplicitDefine); in loadConstant()
151 .addReg(Reg, RegState::ImplicitDefine); in loadConstant()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 37 ImplicitDefine = Implicit | Define, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 346 MIB.addReg(Reg, RegState::ImplicitDefine); in restoreCalleeSavedRegisters()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 42 ImplicitDefine = Implicit | Define, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
600 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
997 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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| D | ARMISelLowering.cpp | 5937 MIB.addReg(SavedRegs[i], RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 707 Mips::FCC0, RegState::ImplicitDefine); in emitCmp()
1884 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead) in fastEmitInst_rr()
1885 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead); in fastEmitInst_rr()
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| D | MipsSEISelDAGToDAG.cpp | 51 IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef; in addDSPCtrlRegOperands()
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| D | MipsSEInstrInfo.cpp | 130 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 446 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
590 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
1403 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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| D | Thumb2InstrInfo.cpp | 205 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| D | ARMBaseInstrInfo.cpp | 1096 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1129 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1150 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1170 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| D | ARMFrameLowering.cpp | 1256 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
1271 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
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| D | ARMLoadStoreOptimizer.cpp | 912 MIB.addReg(ImpDef, RegState::ImplicitDefine); in MergeOpsUpdate()
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| /external/llvm/docs/ |
| D | MIRLangRef.rst | 416 - ``RegState::ImplicitDefine``
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 806 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine | in EmitMachineNode()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 1262 MIB.addReg(*SubRegs, RegState::ImplicitDefine); in toggleKillFlag()
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIParser.cpp | 839 Flags |= RegState::ImplicitDefine; in parseRegisterFlag()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 23540 .addReg(X86::RAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
23548 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
23556 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
23697 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
23709 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
23721 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
24155 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
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| D | X86InstrInfo.cpp | 6099 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
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