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Searched refs:ImplicitDefs (Results 1 – 25 of 30) sorted by relevance

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/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h144 const unsigned *ImplicitDefs; // Registers implicitly defined by this instr variable
234 return ImplicitDefs; in getImplicitDefs()
240 if (ImplicitDefs == 0) return 0; in getNumImplicitDefs()
242 for (; ImplicitDefs[i]; ++i) /*empty*/; in getNumImplicitDefs()
258 if (const unsigned *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h148 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
497 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
501 if (!ImplicitDefs) in getNumImplicitDefs()
504 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
/external/llvm/lib/CodeGen/
DMachineCSE.cpp455 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlock() local
550 ImplicitDefs.push_back(OldReg); in ProcessBlock()
611 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
618 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
646 ImplicitDefs.clear(); in ProcessBlock()
DMachineInstr.cpp639 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DFastISel.cpp1124 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_r()
1146 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rr()
1170 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rrr()
1191 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ri()
1214 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rii()
1235 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rf()
1259 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_rri()
1275 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_i()
1292 ResultReg).addReg(II.ImplicitDefs[0]); in FastEmitInst_ii()
DScheduleDAGFast.cpp426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
509 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
511 for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) { in DelayForLiveRegsBottomUp()
DScheduleDAGSDNodes.cpp117 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { in CheckForPhysRegDependency()
DScheduleDAGRRList.cpp1028 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1112 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
1114 for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) in DelayForLiveRegsBottomUp()
/external/llvm/lib/MC/
DMCInstrDesc.cpp56 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenInstruction.cpp322 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
340 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
343 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
DCodeGenInstruction.h216 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
DDAGISelMatcherGen.cpp782 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
907 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
/external/llvm/utils/TableGen/
DCodeGenInstruction.cpp342 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
371 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
374 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
DCodeGenInstruction.h221 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
DDAGISelMatcherGen.cpp849 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
972 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp301 .addReg(II.ImplicitDefs[0])); in FastEmitInst_r()
323 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rr()
348 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rrr()
370 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ri()
392 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rf()
417 .addReg(II.ImplicitDefs[0])); in FastEmitInst_rri()
436 .addReg(II.ImplicitDefs[0])); in FastEmitInst_i()
456 .addReg(II.ImplicitDefs[0])); in FastEmitInst_ii()
DThumb2SizeReduction.cpp189 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs) in HasImplicitCPSRDef()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1830 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
1855 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
1883 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
1905 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
1930 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
1949 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
1975 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
1991 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
DScheduleDAGFast.cpp441 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
520 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
DScheduleDAGSDNodes.cpp128 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) in CheckForPhysRegDependency()
DScheduleDAGRRList.cpp1197 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1326 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp127 if (const MCPhysReg *R = D.ImplicitDefs) in getDefsUses()
DHexagonVLIWPacketizer.cpp1419 for (const MCPhysReg *P = J->getDesc().ImplicitDefs; P && *P; ++P) { in isLegalToPacketizeTogether()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp295 .addReg(II.ImplicitDefs[0])); in fastEmitInst_r()
323 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rr()
349 .addReg(II.ImplicitDefs[0])); in fastEmitInst_ri()
379 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rri()
398 .addReg(II.ImplicitDefs[0])); in fastEmitInst_i()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineInstr.cpp475 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
476 for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs) in addImplicitDefUseOperands()

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