Searched refs:InputRegs (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 392 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const;
935 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { in getRegSequenceLikeInputs() argument
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| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 1125 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { in getRegSequenceInputs()
1130 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1142 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(), in getRegSequenceInputs()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 56 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
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| D | ARMBaseInstrInfo.cpp | 4597 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { in getRegSequenceLikeInputs()
4609 InputRegs.push_back( in getRegSequenceLikeInputs()
4613 InputRegs.push_back( in getRegSequenceLikeInputs()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 5603 std::set<unsigned> &InputRegs, in MarkAllocatedRegs() argument
5611 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); in MarkAllocatedRegs()
5694 std::set<unsigned> &InputRegs) { in GetRegistersForValue() argument
5794 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); in GetRegistersForValue()
5825 std::set<unsigned> OutputRegs, InputRegs; in visitInlineAsm() local
5989 InputRegs); in visitInlineAsm()
6001 InputRegs); in visitInlineAsm()
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