| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| D | InstCombineSelect.cpp | 842 Value *LHS, *RHS, *LHS2, *RHS2; in visitSelectInst() local
844 if (SelectPatternFlavor SPF2 = MatchSelectPattern(LHS, LHS2, RHS2)) in visitSelectInst()
845 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(LHS),SPF2,LHS2,RHS2, in visitSelectInst()
848 if (SelectPatternFlavor SPF2 = MatchSelectPattern(RHS, LHS2, RHS2)) in visitSelectInst()
849 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(RHS),SPF2,LHS2,RHS2, in visitSelectInst()
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| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSelect.cpp | 1103 Value *LHS, *RHS, *LHS2, *RHS2; in visitSelectInst() local
1138 if (SelectPatternFlavor SPF2 = matchSelectPattern(LHS, LHS2, RHS2).Flavor) in visitSelectInst()
1139 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(LHS),SPF2,LHS2,RHS2, in visitSelectInst()
1142 if (SelectPatternFlavor SPF2 = matchSelectPattern(RHS, LHS2, RHS2).Flavor) in visitSelectInst()
1143 if (Instruction *R = FoldSPFofSPF(cast<Instruction>(RHS),SPF2,LHS2,RHS2, in visitSelectInst()
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| /external/llvm/test/CodeGen/AArch64/ |
| D | cond-sel.ll | 151 ; CHECK: cmp [[LHS2:w[0-9]+]], [[RHS2:w[0-9]+]]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3782 SDValue LHS2 = Op2.getOperand(0); in isSaturatingConditional() local
3793 SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2) in isSaturatingConditional()
3798 SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2; in isSaturatingConditional()
3819 : isLowerSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2) ? &Op2 in isSaturatingConditional()
3824 : isUpperSaturate(LHS2, RHS2, TrueVal2, FalseVal2, CC2, *K2) ? &Op2 in isSaturatingConditional()
4044 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
4046 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
4048 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask); in OptimizeVFPBrcond()
4053 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
8355 unsigned LHS2 = MI.getOperand(2).getReg(); in EmitInstrWithCustomInserter() local
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 2921 SDValue LHS1, LHS2; in OptimizeVFPBrcond() local
2923 expandf64Toi32(LHS, DAG, LHS1, LHS2); in OptimizeVFPBrcond()
2928 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; in OptimizeVFPBrcond()
6190 unsigned LHS2 = MI->getOperand(2).getReg(); in EmitInstrWithCustomInserter() local
6196 .addReg(LHS2).addImm(0) in EmitInstrWithCustomInserter()
6205 .addReg(LHS2).addReg(RHS2) in EmitInstrWithCustomInserter()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 8441 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); in Lower256IntVSETCC() local
8453 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); in Lower256IntVSETCC()
9795 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); in Lower256IntArith() local
9807 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); in Lower256IntArith()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 15119 SDValue LHS2 = extract128BitVector(LHS, NumElems / 2, DAG, dl); in Lower256IntVSETCC() local
15131 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); in Lower256IntVSETCC()
19223 SDValue LHS2 = extract128BitVector(LHS, NumElems / 2, DAG, dl); in Lower256IntArith() local
19235 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); in Lower256IntArith()
19252 SDValue LHS2 = extract256BitVector(LHS, NumElems / 2, DAG, dl); in Lower512IntArith() local
19264 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); in Lower512IntArith()
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