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Searched refs:LWZ (Results 1 – 21 of 21) sorted by relevance

/external/llvm/test/CodeGen/MIR/PowerPC/
Dunordered-implicit-registers.mir38 %1 = LWZ 0, %0 :: (load 4 from %ir.p)
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCInstrInfo.cpp64 case PPC::LWZ: in isLoadFromStackSlot()
504 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), in LoadRegFromStackSlot()
507 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), in LoadRegFromStackSlot()
534 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), in LoadRegFromStackSlot()
DPPCHazardRecognizers.cpp196 case PPC::LWZ: case PPC::LWZU: in getHazardType()
DPPCFrameLowering.cpp603 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) in emitEpilogue()
645 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) in emitEpilogue()
649 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) in emitEpilogue()
DPPCRegisterInfo.cpp79 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
395 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
DPPCInstrInfo.td663 def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
/external/llvm/lib/Target/PowerPC/
DPPCRegisterInfo.cpp68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
394 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) in lowerDynamicAlloc()
554 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRRestore()
641 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), in lowerCRBitRestore()
714 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), in lowerVRSAVERestore()
DPPCAsmPrinter.cpp542 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
572 TmpInst.setOpcode(PPC::LWZ); in EmitInstruction()
777 TmpInst.setOpcode(isPPC64 ? PPC::LD : PPC::LWZ); in EmitInstruction()
807 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::LWZ) in EmitInstruction()
DPPCInstrInfo.cpp269 case PPC::LWZ: in isLoadFromStackSlot()
1101 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ), in LoadRegFromStackSlot()
1869 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
DPPCFrameLowering.cpp1137 : PPC::LWZ ); in emitEpilogue()
1794 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), in restoreCRs()
DPPCFastISel.cpp498 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) : in PPCEmitLoad()
574 case PPC::LWZ: Opc = PPC::LWZX; break; in PPCEmitLoad()
DPPCISelLowering.cpp8827 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP) in emitEHSjLjLongJmp()
8839 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp) in emitEHSjLjLongJmp()
8851 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP) in emitEHSjLjLongJmp()
8863 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP) in emitEHSjLjLongJmp()
DPPCISelDAGToDAG.cpp4286 case PPC::LWZ: in PeepholePPC64()
DPPCInstrInfo.td1651 def LWZ : DForm_1<32, (outs gprc:$rD), (ins memri:$src),
4205 def : Pat<(atomic_load_32 iaddr:$src), (LWZ memri:$src)>;
/external/llvm/test/CodeGen/PowerPC/
Dno-rlwimi-trivial-commute.mir78 %2 = LWZ 0, %1 :: (load 4 from %ir.0)
/external/v8/src/ppc/
Dassembler-ppc-inl.h482 const uint32_t kLoadIntptrOpcode = LWZ;
Ddisasm-ppc.cc1297 case LWZ: { in InstructionDecode()
Dconstants-ppc.h1721 V(lwz, LWZ, 0x80000000) \
Dassembler-ppc.cc1200 d_form(LWZ, dst, src.ra(), src.offset(), true); in lwz()
Dsimulator-ppc.cc3693 case LWZ: { in ExecuteGeneric()
/external/pcre/dist2/src/sljit/
DsljitNativePPC_common.c181 #define LWZ (HI(32)) macro
572 #define STACK_LOAD LWZ