Home
last modified time | relevance | path

Searched refs:MCOperand (Results 1 – 25 of 163) sorted by relevance

1234567

/external/llvm/test/MC/Lanai/
Dmemory.s10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
Dconditional_inst.s10 ! CHECK-NEXT: <MCOperand Reg:12>>
16 ! CHECK-NEXT: <MCOperand Imm:4660>
22 ! CHECK-NEXT: <MCOperand Imm:2000>
23 ! CHECK-NEXT: <MCOperand Imm:13>
30 ! CHECK-NEXT: <MCOperand Expr:(jump1)>
31 ! CHECK-NEXT: <MCOperand Imm:13>
37 ! CHECK-NEXT: <MCOperand Expr:(jump2)>
38 ! CHECK-NEXT: <MCOperand Imm:10>
46 ! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)>
52 ! CHECK-NEXT: <MCOperand Reg:26>
[all …]
/external/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.h26 class MCOperand; variable
46 MCOperand createRegOperand(unsigned int RegId) const;
47 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
48 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
50 MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
57 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
58 MCOperand decodeOperand_VS_32(unsigned Val) const;
59 MCOperand decodeOperand_VS_64(unsigned Val) const;
61 MCOperand decodeOperand_VReg_64(unsigned Val) const;
62 MCOperand decodeOperand_VReg_96(unsigned Val) const;
[all …]
DAMDGPUDisassembler.cpp44 addOperand(MCInst &Inst, const MCOperand& Opnd) { in addOperand()
169 MCOperand AMDGPUDisassembler::errOperand(unsigned V, in errOperand()
175 return MCOperand(); in errOperand()
179 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { in createRegOperand()
180 return MCOperand::createReg(RegId); in createRegOperand()
184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand()
194 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, in createSRegOperand()
229 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { in decodeOperand_VS_32()
233 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { in decodeOperand_VS_64()
237 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { in decodeOperand_VGPR_32()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMAsmPrinter.cpp984 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); in EmitJump2Table()
985 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitJump2Table()
986 BrInst.addOperand(MCOperand::CreateReg(0)); in EmitJump2Table()
1031 Inst.addOperand(MCOperand::CreateReg(Dest)); in populateADROperands()
1032 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); in populateADROperands()
1034 Inst.addOperand(MCOperand::CreateImm(pred)); in populateADROperands()
1035 Inst.addOperand(MCOperand::CreateReg(ccreg)); in populateADROperands()
1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); in EmitInstruction()
1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); in EmitInstruction()
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
[all …]
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp577 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
583 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
622 MI.addOperand(MCOperand::createImm(Imm)); in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
/external/llvm/include/llvm/MC/
DMCInst.h33 class MCOperand {
53 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} in MCOperand() function
111 static MCOperand createReg(unsigned Reg) { in createReg()
112 MCOperand Op; in createReg()
117 static MCOperand createImm(int64_t Val) { in createImm()
118 MCOperand Op; in createImm()
123 static MCOperand createFPImm(double Val) { in createFPImm()
124 MCOperand Op; in createFPImm()
129 static MCOperand createExpr(const MCExpr *Val) { in createExpr()
130 MCOperand Op; in createExpr()
[all …]
DMCInstBuilder.h33 Inst.addOperand(MCOperand::createReg(Reg)); in addReg()
39 Inst.addOperand(MCOperand::createImm(Val)); in addImm()
45 Inst.addOperand(MCOperand::createFPImm(Val)); in addFPImm()
51 Inst.addOperand(MCOperand::createExpr(Val)); in addExpr()
57 Inst.addOperand(MCOperand::createInst(Val)); in addInst()
62 MCInstBuilder &addOperand(const MCOperand &Op) { in addOperand()
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInst.h31 class MCOperand {
49 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} in MCOperand() function
97 static MCOperand CreateReg(unsigned Reg) { in CreateReg()
98 MCOperand Op; in CreateReg()
103 static MCOperand CreateImm(int64_t Val) { in CreateImm()
104 MCOperand Op; in CreateImm()
109 static MCOperand CreateFPImm(double Val) { in CreateFPImm()
110 MCOperand Op; in CreateFPImm()
115 static MCOperand CreateExpr(const MCExpr *Val) { in CreateExpr()
116 MCOperand Op; in CreateExpr()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86Disassembler.cpp161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
256 mcInst.addOperand(MCOperand::CreateImm(immediate)); in translateImmediate()
287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; in translateRMRegister()
316 MCOperand baseReg; in translateRMMemory()
317 MCOperand scaleAmount; in translateRMMemory()
318 MCOperand indexReg; in translateRMMemory()
319 MCOperand displacement; in translateRMMemory()
320 MCOperand segmentReg; in translateRMMemory()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp60 const MCOperand &Dst = MI->getOperand(0); in printInst()
61 const MCOperand &MO1 = MI->getOperand(1); in printInst()
62 const MCOperand &MO2 = MI->getOperand(2); in printInst()
63 const MCOperand &MO3 = MI->getOperand(3); in printInst()
80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst()
201 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
226 const MCOperand &MO1 = MI->getOperand(OpNum); in printT2LdrLabelOperand()
242 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand()
[all …]
/external/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp77 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
82 return MCOperand::createExpr(expr); in createSparcMCOperand()
85 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
90 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
105 return MCOperand::createExpr(expr); in createPCXRelExprOp()
109 MCOperand &Callee, in EmitCall()
119 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
130 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
142 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
148 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
[all …]
DSparcMCInstLower.cpp30 static MCOperand LowerSymbolOperand(const MachineInstr *MI, in LowerSymbolOperand()
65 return MCOperand::createExpr(expr); in LowerSymbolOperand()
68 static MCOperand LowerOperand(const MachineInstr *MI, in LowerOperand()
76 return MCOperand::createReg(MO.getReg()); in LowerOperand()
79 return MCOperand::createImm(MO.getImm()); in LowerOperand()
91 return MCOperand(); in LowerOperand()
103 MCOperand MCOp = LowerOperand(MI, MO, AP); in LowerSparcMachineInstrToMCInst()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp538 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
539 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
540 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
546 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
547 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
548 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
558 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
559 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
564 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
565 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp191 MCStreamer &OutStreamer, const MCOperand &Imm, in smallData()
266 MCOperand Reg = Inst.getOperand(0); in HexagonProcessInstruction()
267 MCOperand S16 = Inst.getOperand(1); in HexagonProcessInstruction()
272 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
281 const MCOperand &Imm = MappedInst.getOperand(1); in HexagonProcessInstruction()
288 MCOperand &Reg = MappedInst.getOperand(0); in HexagonProcessInstruction()
291 TmpInst.addOperand(MCOperand::createExpr( in HexagonProcessInstruction()
302 MCOperand &Imm = MappedInst.getOperand(1); in HexagonProcessInstruction()
307 MCOperand &Reg = MappedInst.getOperand(0); in HexagonProcessInstruction()
310 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in HexagonProcessInstruction()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
402 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
433 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
434 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues()
462 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
498 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLTargetOpValue()
510 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLXTargetOpValue()
521 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBRTargetOpValue()
532 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBCCTargetOpValue()
543 const MCOperand MO = MI.getOperand(OpIdx); in getThumbCBTargetOpValue()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
277 const MCOperand &MO = MI.getOperand(Op); in getSOImmOpValue()
310 const MCOperand &MO = MI.getOperand(Op); in getModImmOpValue()
522 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
554 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
555 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues()
584 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
621 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLTargetOpValue()
634 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBLXTargetOpValue()
646 const MCOperand MO = MI.getOperand(OpIdx); in getThumbBRTargetOpValue()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst()
83 const MCOperand &MO3 = MI->getOperand(3); in printInst()
103 const MCOperand &Dst = MI->getOperand(0); in printInst()
104 const MCOperand &MO1 = MI->getOperand(1); in printInst()
105 const MCOperand &MO2 = MI->getOperand(2); in printInst()
247 MCOperand NewReg; in printInst()
252 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg( in printInst()
274 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
[all …]
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp354 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
359 Inst.addOperand(MCOperand::createExpr(getImm())); in addImmOperands()
368 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
374 Inst.addOperand(MCOperand::createExpr(Expr)); in addSignedImmOperands()
558 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); in adds4_6ImmOperands()
565 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64)); in adds3_6ImmOperands()
756 for (MCOperand &I : MCI) in canonicalizeImmediates()
759 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create( in canonicalizeImmediates()
826 MCB.addOperand(MCOperand::createImm(0)); in MatchAndEmitInstruction()
855 MCB.addOperand(MCOperand::createInst(SubInst)); in MatchAndEmitInstruction()
[all …]
/external/llvm/lib/Target/X86/Disassembler/
DX86Disassembler.cpp257 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
325 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
328 MCOperand segmentReg; in translateSrcIndex()
329 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
350 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
616 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
619 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
622 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
625 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); in translateImmediate()
653 mcInst.addOperand(MCOperand::createImm(immediate)); in translateImmediate()
[all …]
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiMCCodeEmitter.cpp58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
113 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups, in getMachineOpValue()
140 const MCOperand AluOp = Inst.getOperand(3); in adjustPqBits()
145 const MCOperand Op2 = Inst.getOperand(2); in adjustPqBits()
192 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRiMemoryOpValue()
193 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRiMemoryOpValue()
194 const MCOperand AluOp = Inst.getOperand(OpNo + 2); in getRiMemoryOpValue()
224 const MCOperand Op1 = Inst.getOperand(OpNo + 0); in getRrMemoryOpValue()
225 const MCOperand Op2 = Inst.getOperand(OpNo + 1); in getRrMemoryOpValue()
226 const MCOperand AluMCOp = Inst.getOperand(OpNo + 2); in getRrMemoryOpValue()
[all …]
/external/llvm/lib/Target/Lanai/InstPrinter/
DLanaiInstPrinter.cpp149 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
162 const MCOperand &Op = MI->getOperand(OpNo); in printMemImmOperand()
176 const MCOperand &Op = MI->getOperand(OpNo); in printHi16ImmOperand()
188 const MCOperand &Op = MI->getOperand(OpNo); in printHi16AndImmOperand()
200 const MCOperand &Op = MI->getOperand(OpNo); in printLo16AndImmOperand()
211 const MCOperand &RegOp) { in printMemoryBaseRegister()
224 const MCOperand &OffsetOp, in printMemoryImmediateOffset()
237 const MCOperand &RegOp = MI->getOperand(OpNo); in printMemRiOperand()
238 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); in printMemRiOperand()
239 const MCOperand &AluOp = MI->getOperand(OpNo + 2); in printMemRiOperand()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreMCInstLower.cpp35 MCOperand XCoreMCInstLower::LowerSymbolOperand(const MachineOperand &MO, in LowerSymbolOperand()
71 return MCOperand::createExpr(MCSym); in LowerSymbolOperand()
78 return MCOperand::createExpr(Add); in LowerSymbolOperand()
81 MCOperand XCoreMCInstLower::LowerOperand(const MachineOperand &MO, in LowerOperand()
90 return MCOperand::createReg(MO.getReg()); in LowerOperand()
92 return MCOperand::createImm(MO.getImm() + offset); in LowerOperand()
104 return MCOperand(); in LowerOperand()
112 MCOperand MCOp = LowerOperand(MO); in Lower()
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
186 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue()
200 const MCOperand &MO = MI.getOperand(OpIdx); in getLdStUImm12OpValue()
221 const MCOperand &MO = MI.getOperand(OpIdx); in getAdrLabelOpValue()
248 const MCOperand &MO = MI.getOperand(OpIdx); in getAddSubImmOpValue()
249 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue()
274 const MCOperand &MO = MI.getOperand(OpIdx); in getCondBranchTargetOpValue()
296 const MCOperand &MO = MI.getOperand(OpIdx); in getLoadLiteralOpValue()
325 const MCOperand &MO = MI.getOperand(OpIdx); in getMoveWideImmOpValue()
344 const MCOperand &MO = MI.getOperand(OpIdx); in getTestBranchTargetOpValue()
[all …]
/external/llvm/lib/Target/SystemZ/Disassembler/
DSystemZDisassembler.cpp83 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
157 Inst.addOperand(MCOperand::createImm(Imm)); in decodeUImmOperand()
165 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); in decodeSImmOperand()
245 Inst.addOperand(MCOperand::createImm(Value)); in decodePCDBLOperand()
273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
274 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDAddr12Operand()
283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
284 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp))); in decodeBDAddr20Operand()
294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
295 Inst.addOperand(MCOperand::createImm(Disp)); in decodeBDXAddr12Operand()
[all …]

1234567