| /external/llvm/lib/Target/Mips/ |
| D | MipsOptionRecord.h | 64 const MCRegisterClass *GPR32RegClass;
65 const MCRegisterClass *GPR64RegClass;
66 const MCRegisterClass *FGR32RegClass;
67 const MCRegisterClass *FGR64RegClass;
68 const MCRegisterClass *AFGR64RegClass;
69 const MCRegisterClass *MSA128BRegClass;
70 const MCRegisterClass *COP0RegClass;
71 const MCRegisterClass *COP2RegClass;
72 const MCRegisterClass *COP3RegClass;
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 25 class MCRegisterClass {
39 MCRegisterClass(unsigned id, const char *name, in MCRegisterClass() function
138 typedef const MCRegisterClass *regclass_iterator;
143 const MCRegisterClass *Classes; // Pointer to the regclass array
155 const MCRegisterClass *C, unsigned NC) { in InitMCRegisterInfo()
299 const MCRegisterClass getRegClass(unsigned i) const { in getRegClass()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 30 class MCRegisterClass {
137 typedef const MCRegisterClass *regclass_iterator;
159 const MCRegisterClass *Classes; // Pointer to the regclass array
247 const MCRegisterClass *C, unsigned NC, in InitMCRegisterInfo()
348 const MCRegisterClass *RC) const;
417 const MCRegisterClass& getRegClass(unsigned i) const { in getRegClass()
422 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName()
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| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 214 const MCRegisterClass &RC = MRI.getRegClass(RCID); in encodeInstruction()
284 const MCRegisterClass &RC = MRI.getRegClass(RCID); in getMachineOpValue()
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 41 const MCRegisterClass *MC;
47 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts, in TargetRegisterClass()
|
| /external/llvm/lib/MC/ |
| D | MCRegisterInfo.cpp | 19 const MCRegisterClass *RC) const { in getMatchingSuperReg()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 14 class MCRegisterClass;
15 extern MCRegisterClass X86MCRegisterClasses[];
1130 MCRegisterClass X86MCRegisterClasses[] = {
1131 MCRegisterClass(X86::GR8RegClassID, "GR8", 1, 1, 1, 1, GR8, GR8 + 20, GR8Bits, sizeof(GR8Bits)),
1132 …MCRegisterClass(X86::GR64RegClassID, "GR64", 8, 8, 1, 1, GR64, GR64 + 17, GR64Bits, sizeof(GR64Bit…
1133 …MCRegisterClass(X86::GR16RegClassID, "GR16", 2, 2, 1, 1, GR16, GR16 + 16, GR16Bits, sizeof(GR16Bit…
1134 …MCRegisterClass(X86::GR32RegClassID, "GR32", 4, 4, 1, 1, GR32, GR32 + 16, GR32Bits, sizeof(GR32Bit…
1135 …MCRegisterClass(X86::FR32RegClassID, "FR32", 4, 4, 1, 1, FR32, FR32 + 16, FR32Bits, sizeof(FR32Bit…
1136 …MCRegisterClass(X86::GR64_with_sub_8bitRegClassID, "GR64_with_sub_8bit", 8, 8, 1, 1, GR64_with_sub…
1137 …MCRegisterClass(X86::FR64RegClassID, "FR64", 8, 8, 1, 1, FR64, FR64 + 16, FR64Bits, sizeof(FR64Bit…
[all …]
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 388 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID); in printOperand()
409 const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass); in printOperand()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 63 const MCRegisterClass *MC;
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | pr15031.ll | 96 …type { %"struct.llvm::MCRegisterDesc"*, i32, i32, i32, %"class.llvm::MCRegisterClass"*, i32, i32, …
98 %"class.llvm::MCRegisterClass" = type { i8*, i16*, i8*, i16, i16, i16, i16, i16, i8, i8 }
201 %"class.llvm::TargetRegisterClass" = type { %"class.llvm::MCRegisterClass"*, i32*, i32*, i16*, %"cl…
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1315 const MCRegisterClass &FPR128RC = in printVectorList()
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 242 const MCRegisterClass &MRC = MRI.getRegClass(ARM::GPRRegClassID); in printInst()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4620 const MCRegisterClass &WRegClass = in tryParseGPRSeqPair()
4622 const MCRegisterClass &XRegClass = in tryParseGPRSeqPair()
|
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 935 const MCRegisterClass RC = TRI->getRegClass(RCID); in ParseAMDGPURegister()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3474 const MCRegisterClass *RC; in parseRegisterList()
3850 const MCRegisterClass *RC = (Spacing == 1) ? in parseVectorList()
3863 const MCRegisterClass *RC = (Spacing == 1) ? in parseVectorList()
6035 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID); in ParseInstruction()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2191 MCRegisterClass *RC; in parseRegisterList()
|