Searched refs:MI2 (Results 1 – 9 of 9) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| D | TargetInstrInfo.cpp | 571 MachineInstr *MI2 = nullptr; in hasReassociableOperands() local
575 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
578 return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB; in hasReassociableOperands()
586 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling() local
591 Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode; in hasReassociableSibling()
593 std::swap(MI1, MI2); in hasReassociableSibling()
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| D | MachineInstr.cpp | 905 static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) { in hasIdenticalMMOs() argument
907 auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end(); in hasIdenticalMMOs()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 249 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
253 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
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| /external/clang/test/Analysis/ |
| D | padding_cpp.cpp | 102 class MI2 : public PaddedA, public InnerPaddedB { // xxxexpected-warning{{Excessive padding in 'cla… class
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| /external/llvm/lib/Target/X86/ |
| D | X86OptimizeLEAs.cpp | 250 const MachineInstr &MI2, unsigned N2) const;
365 const MachineInstr &MI2, in getAddrDispShift() argument
368 const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp); in getAddrDispShift()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.h | 97 bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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| D | HexagonVLIWPacketizer.cpp | 845 MachineInstr &MI2) { in arePredicatesComplements() argument
849 getPredicateSense(MI2, HII) == PK_Unknown) in arePredicatesComplements()
902 unsigned PReg2 = getPredicatedRegister(MI2, HII); in arePredicatesComplements()
906 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) && in arePredicatesComplements()
907 HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2); in arePredicatesComplements()
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| D | HexagonInstrInfo.cpp | 2933 const MachineInstr *MI2) const { in addLatencyToSchedule()
2934 if (isV60VectorInstruction(MI1) && isV60VectorInstruction(MI2)) in addLatencyToSchedule()
2935 if (!isVecUsableNextPacket(MI1, MI2)) in addLatencyToSchedule()
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| /external/llvm/lib/Target/ARM/ |
| D | MLxExpansionPass.cpp | 317 MachineInstr &MI2 = *MII; in ExpandFPMLxInstruction()
321 dbgs() << " " << MI2; in ExpandFPMLxInstruction()
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