| /external/llvm/lib/Target/X86/ |
| D | X86WinAllocaExpander.cpp | 92 (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) || in getWinAllocaAmount()
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| D | X86InstrCompiler.td | 291 // AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1.
1063 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
1065 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
1067 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
1069 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
1071 (MOV64ri mcsym:$dst)>, Requires<[FarData]>;
1073 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
1114 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
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| D | X86FrameLowering.cpp | 271 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri; in emitSPUpdate()
737 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11) in emitStackProbeCall()
1183 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) in emitPrologue()
2261 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri; in adjustForSegmentedStacks()
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| D | X86FastISel.cpp | 3520 Opc = X86::MOV64ri; in X86MaterializeInt()
3595 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri), in X86MaterializeFP()
3633 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri), in X86MaterializeGV()
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| D | X86MCInstLower.cpp | 1014 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); in LowerPATCHPOINT()
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| D | X86InstrInfo.td | 1384 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
2965 def : InstAlias<"movq\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>;
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| D | X86InstrInfo.cpp | 5456 : X86::MOV64ri)); in ExpandMOVImmSExti8()
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| D | X86ISelLowering.cpp | 18764 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. in LowerINIT_TRAMPOLINE() local
18772 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 in LowerINIT_TRAMPOLINE()
18786 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 in LowerINIT_TRAMPOLINE()
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| D | X86InstrAVX512.td | 923 (VPBROADCASTQrZrkz VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 842 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) in emitPrologue()
856 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11) in emitPrologue()
1411 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10) in adjustForSegmentedStacks()
1413 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11) in adjustForSegmentedStacks()
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| D | X86InstrCompiler.td | 863 (MOV64ri tconstpool :$dst)>, Requires<[FarData]>;
865 (MOV64ri tjumptable :$dst)>, Requires<[FarData]>;
867 (MOV64ri tglobaladdr :$dst)>, Requires<[FarData]>;
869 (MOV64ri texternalsym:$dst)>, Requires<[FarData]>;
871 (MOV64ri tblockaddress:$dst)>, Requires<[FarData]>;
927 (MOV64ri tglobaltlsaddr :$dst)>;
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| D | X86CodeEmitter.cpp | 838 if (Opcode == X86::MOV64ri) in emitInstruction()
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| D | X86InstrInfo.td | 864 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
1698 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>;
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| D | X86GenAsmWriter.inc | 1477 1145050699U, // MOV64ri
6018 "64rc\000MOV64rd\000MOV64ri\000MOV64ri32\000MOV64ri64i32\000MOV64rm\000M"
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| D | X86ISelLowering.cpp | 9511 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. in LowerINIT_TRAMPOLINE() local
9519 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 in LowerINIT_TRAMPOLINE()
9533 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 in LowerINIT_TRAMPOLINE()
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| D | X86GenAsmWriter1.inc | 1477 139333952U, // MOV64ri
6761 "64rc\000MOV64rd\000MOV64ri\000MOV64ri32\000MOV64ri64i32\000MOV64rm\000M"
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| D | X86GenDisassemblerTables.inc | 17587 "MOV64ri"
83294 0x5b8 /* MOV64ri*/
83298 0x5b8 /* MOV64ri*/
83302 0x5b8 /* MOV64ri*/
83306 0x5b8 /* MOV64ri*/
83310 0x5b8 /* MOV64ri*/
83314 0x5b8 /* MOV64ri*/
83318 0x5b8 /* MOV64ri*/
83322 0x5b8 /* MOV64ri*/
111375 0x5b8 /* MOV64ri*/
[all …]
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| D | X86GenAsmMatcher.inc | 3826 { X86::MOV64ri, "movabsq", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR64 }, 0},
3948 { X86::MOV64ri, "movq", Convert__Reg1_1__Imm1_0, { MCK_Imm, MCK_GR64 }, 0},
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| D | X86GenInstrInfo.inc | 1480 MOV64ri = 1464,
5648 …, 0, 0, "MOV64ri", 0|(1<<MCID::Rematerializable)|(1<<MCID::CheapAsAMove), 0x17001e002ULL, NULL, NU…
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| D | X86GenDAGISel.inc | 36137 /*74955*/ OPC_MorphNodeTo, TARGET_VAL(X86::MOV64ri), 0,
36140 // Dst: (MOV64ri:i64 (imm:i64):$src)
36175 /*75031*/ OPC_MorphNodeTo, TARGET_VAL(X86::MOV64ri), 0,
36178 // Dst: (MOV64ri:i64 (tconstpool:i64):$dst)
36203 /*75084*/ OPC_MorphNodeTo, TARGET_VAL(X86::MOV64ri), 0,
36206 // Dst: (MOV64ri:i64 (tjumptable:i64):$dst)
36229 /*75133*/ OPC_MorphNodeTo, TARGET_VAL(X86::MOV64ri), 0,
36232 // Dst: (MOV64ri:i64 (tglobaltlsaddr:i64):$dst)
36244 /*75163*/ OPC_MorphNodeTo, TARGET_VAL(X86::MOV64ri), 0,
36247 // Dst: (MOV64ri:i64 (tglobaladdr:i64):$dst)
[all …]
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| D | X86GenFastISel.inc | 4879 return FastEmitInst_i(X86::MOV64ri, X86::GR64RegisterClass, imm0);
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| /external/llvm/test/CodeGen/X86/ |
| D | implicit-null-checks.mir | 249 %rdi = MOV64ri 5000
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1860 if (Opcode == X86::MOV64ri)
|