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Searched refs:MRM1r (Results 1 – 22 of 22) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h215 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
490 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp578 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
964 case X86II::MRM0r: case X86II::MRM1r: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td506 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
509 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
512 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
515 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
520 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
523 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
527 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
530 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
536 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
539 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrSystem.td217 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
219 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
221 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
455 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
457 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
DX86InstrArithmetic.td412 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
416 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
463 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
475 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
1089 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
DX86CodeEmitter.cpp901 case X86II::MRM0r: case X86II::MRM1r: in emitInstruction()
DX86InstrFormats.td25 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
DX86InstrCompiler.td549 def Int_MemBarrierNoSSE64 : RI<0x09, MRM1r, (outs), (ins GR64:$zero),
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td578 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
581 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
584 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
587 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
592 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
595 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
599 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
603 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
610 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
614 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrSystem.td245 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
247 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
249 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
579 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
582 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
DX86InstrFPStack.td279 def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t$op">;
280 def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st(0), $op|$op, st(0)}">;
281 def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t$op">;
387 def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RST:$op),
395 def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RST:$op),
542 def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RST:$op), "fxch\t$op", IIC_FXCH>;
DX86InstrArithmetic.td501 def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
506 def DEC16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
510 def DEC32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
514 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
1193 defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m,
DX86InstrInfo.td2220 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
2221 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
2396 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
2399 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
DX86InstrFormats.td30 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
DX86InstrAVX512.td4259 defm VPROL : avx512_shift_rmi_dq<0x72, 0x72, MRM1r, MRM1m, "vprol", X86vrotli>, AVX512BIi8Base, EVE…
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
728 case X86Local::MRM1r: in emitInstructionSpecifier()
820 case X86Local::MRM1r: in emitDecodePath()
909 case X86Local::MRM1r: in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h295 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, // Format /0 /1 /2 /3 enumerator
685 case X86II::MRM0r: case X86II::MRM1r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp869 case X86II::MRM0r: case X86II::MRM1r: in EmitVEXOpcodePrefix()
1020 case X86II::MRM0r: case X86II::MRM1r: in DetermineREXPrefix()
1355 case X86II::MRM0r: case X86II::MRM1r: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, enumerator
716 case X86Local::MRM1r: in emitInstructionSpecifier()
852 case X86Local::MRM0r: case X86Local::MRM1r: in emitDecodePath()
/external/llvm/test/TableGen/
DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td52 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1818 case X86II::MRM0r: case X86II::MRM1r: // for instructions that operate on