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Searched refs:MRM4r (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86InstrControl.td135 def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
142 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
149 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
260 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
310 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
322 def TAILJMPr64_REX : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst),
DX86InstrShiftRotate.td20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
47 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
57 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
59 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrSystem.td378 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
448 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
450 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
453 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
DX86InstrFPStack.td274 def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t$op">;
275 def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st(0), $op|$op, st(0)}">;
276 def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t$op">;
589 def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
DX86InstrMMX.td505 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
508 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
DX86InstrArithmetic.td61 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
69 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
74 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
80 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
1191 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
DX86InstrInfo.td1638 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1642 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1646 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
2404 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
DX86InstrFormats.td31 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
DX86InstrSSE.td4057 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4069 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4108 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4120 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4164 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4167 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h216 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
492 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp580 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
966 case X86II::MRM4r: case X86II::MRM5r: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
45 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
52 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
54 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
DX86InstrControl.td101 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
106 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
199 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops),
298 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst, variable_ops),
DX86InstrSystem.td326 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
379 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
381 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
384 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
DX86InstrMMX.td318 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
320 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
DX86InstrArithmetic.td49 def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
57 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
62 def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
66 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
1087 defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m,
DX86CodeEmitter.cpp903 case X86II::MRM4r: case X86II::MRM5r: in emitInstruction()
DX86InstrFormats.td26 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
DX86InstrInfo.td1026 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
1030 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
1033 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
/external/llvm/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
109 "shl $dst, CL", 0xD2, MRM4r,
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td53 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
109 "shl $dst, CL", 0xD2, MRM4r,
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
731 case X86Local::MRM4r: in emitInstructionSpecifier()
823 case X86Local::MRM4r: in emitDecodePath()
912 case X86Local::MRM4r: in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h296 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, // Format /4 /5 /6 /7 enumerator
687 case X86II::MRM4r: case X86II::MRM5r: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp871 case X86II::MRM4r: case X86II::MRM5r: in EmitVEXOpcodePrefix()
1022 case X86II::MRM4r: case X86II::MRM5r: in DetermineREXPrefix()
1357 case X86II::MRM4r: case X86II::MRM5r: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, enumerator
719 case X86Local::MRM4r: in emitInstructionSpecifier()
854 case X86Local::MRM4r: case X86Local::MRM5r: in emitDecodePath()

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