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Searched refs:MRM5m (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h220 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 enumerator
497 case X86II::MRM4m: case X86II::MRM5m: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp545 case X86II::MRM4m: case X86II::MRM5m: in EmitVEXOpcodePrefix()
680 case X86II::MRM4m: case X86II::MRM5m: in DetermineREXPrefix()
977 case X86II::MRM4m: case X86II::MRM5m: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td155 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
158 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
162 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
165 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
169 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
172 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
176 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
179 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
184 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
187 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
[all …]
DX86InstrControl.td117 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
120 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
122 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
DX86InstrSystem.td332 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
416 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
418 def XRSTOR64 : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
DX86InstrFPStack.td212 defm SUBR: FPBinary<fsub ,MRM5m, "subr">;
421 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
424 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
553 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
DX86CodeEmitter.cpp208 case X86II::MRM4m: case X86II::MRM5m: in determineREX()
938 case X86II::MRM4m: case X86II::MRM5m: in emitInstruction()
DX86InstrArithmetic.td110 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
113 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
116 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
119 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
1095 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
DX86InstrFormats.td29 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
DX86InstrInfo.td1122 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1124 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1126 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
DX86InstrCompiler.td641 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">;
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td173 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
176 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
180 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
184 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
188 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, u8imm:$src),
192 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, u8imm:$src),
196 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, u8imm:$src),
200 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, u8imm:$src),
206 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
210 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
[all …]
DX86InstrControl.td166 def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
170 def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
173 def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
DX86InstrSystem.td384 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
495 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
498 def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
519 def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
522 def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
DX86InstrFPStack.td246 defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>;
474 def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src",
480 def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src",
624 def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
DX86InstrArithmetic.td131 def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
135 def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
140 def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
145 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
1200 defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m,
DX86InstrInfo.td1793 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1796 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1799 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
2398 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
DX86InstrFormats.td34 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
DX86InstrAVX512.td6818 defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
6821 defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
6824 defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
6827 defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, enumerator
753 case X86Local::MRM5m: in emitInstructionSpecifier()
834 case X86Local::MRM5m: in emitDecodePath()
923 case X86Local::MRM5m: in emitDecodePath()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h300 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 enumerator
693 case X86II::MRM4m: case X86II::MRM5m: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp784 case X86II::MRM4m: case X86II::MRM5m: in EmitVEXOpcodePrefix()
1014 case X86II::MRM4m: case X86II::MRM5m: in DetermineREXPrefix()
1373 case X86II::MRM4m: case X86II::MRM5m: in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp111 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, enumerator
745 case X86Local::MRM5m: in emitInstructionSpecifier()
860 case X86Local::MRM4m: case X86Local::MRM5m: in emitDecodePath()
/external/llvm/test/TableGen/
DTargetInstrInfo.td56 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td56 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;

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