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Searched refs:MRM7m (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h220 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 enumerator
498 case X86II::MRM6m: case X86II::MRM7m: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp546 case X86II::MRM6m: case X86II::MRM7m: in EmitVEXOpcodePrefix()
681 case X86II::MRM6m: case X86II::MRM7m: in DetermineREXPrefix()
978 case X86II::MRM6m: case X86II::MRM7m: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td245 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
248 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
251 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
254 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
258 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
261 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
265 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
268 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
273 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
276 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
[all …]
DX86InstrVMX.td38 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
DX86InstrFPStack.td215 defm DIVR: FPBinary<fdiv, MRM7m, "divr">;
289 def FNSTSWm : FPI<0xDD, MRM7m, (outs f32mem:$dst), (ins), "fnstsw\t$dst">;
431 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
436 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
548 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
DX86CodeEmitter.cpp209 case X86II::MRM6m: case X86II::MRM7m: in determineREX()
939 case X86II::MRM6m: case X86II::MRM7m: { in emitInstruction()
DX86InstrArithmetic.td291 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
294 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
297 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
300 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
1106 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
DX86InstrSystem.td215 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
DX86InstrFormats.td30 def MRM6m : Format<30>; def MRM7m : Format<31>;
DX86InstrInfo.td1072 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1074 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1076 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
DX86InstrSSE.td3183 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, enumerator
138 (form >= X86Local::MRM0m && form <= X86Local::MRM7m)) in needsModRMForDecode()
755 case X86Local::MRM7m: in emitInstructionSpecifier()
836 case X86Local::MRM7m: in emitDecodePath()
925 case X86Local::MRM7m: in emitDecodePath()
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td284 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
288 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
292 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
296 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
301 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, u8imm:$src),
305 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, u8imm:$src),
309 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, u8imm:$src),
313 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, u8imm:$src),
319 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
323 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
[all …]
DX86InstrVMX.td44 def VMPTRSTm : I<0xC7, MRM7m, (outs), (ins i64mem:$vmcs),
DX86InstrFPStack.td253 defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>;
339 def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;
492 def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst",
502 def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst",
619 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
DX86InstrArithmetic.td351 def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
355 def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
359 def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
363 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
1211 defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>;
DX86InstrInfo.td1705 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
1708 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
1711 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
2403 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
2516 def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
DX86InstrSystem.td242 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
DX86InstrFormats.td35 def MRM6m : Format<30>; def MRM7m : Format<31>;
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h300 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, // Format /4 /5 /6 /7 enumerator
694 case X86II::MRM6m: case X86II::MRM7m: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp785 case X86II::MRM6m: case X86II::MRM7m: { in EmitVEXOpcodePrefix()
1015 case X86II::MRM6m: case X86II::MRM7m: in DetermineREXPrefix()
1374 case X86II::MRM6m: case X86II::MRM7m: { in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp111 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, enumerator
747 case X86Local::MRM7m: in emitInstructionSpecifier()
861 case X86Local::MRM6m: case X86Local::MRM7m: in emitDecodePath()
/external/llvm/test/TableGen/
DTargetInstrInfo.td57 def MRM6m : Format<30>; def MRM7m : Format<31>;
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td57 def MRM6m : Format<30>; def MRM7m : Format<31>;
/external/llvm/docs/
DWritingAnLLVMBackend.rst1827 case X86II::MRM6m: case X86II::MRM7m: // to hold extended opcode data

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