Home
last modified time | relevance | path

Searched refs:MRMDestReg (Results 1 – 25 of 30) sorted by relevance

12

/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrVMX.td42 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
46 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
DX86InstrInfo.td845 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
847 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
849 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
851 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
966 def MOV8rr_NOREX : I<0x88, MRMDestReg,
992 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
995 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
998 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1054 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1056 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
[all …]
DX86InstrSystem.td115 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
117 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
128 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
130 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
153 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
155 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
157 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
DX86InstrShiftRotate.td601 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
606 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
611 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
615 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
619 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
624 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
632 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
639 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
646 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
653 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
[all …]
DX86InstrSSE.td345 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
349 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
379 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
382 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
719 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
722 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
725 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
728 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
731 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
734 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
[all …]
DX86InstrMMX.td158 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
171 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
DX86InstrExtension.td144 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
DX86CodeEmitter.cpp853 case X86II::MRMDestReg: { in emitInstruction()
/external/llvm/test/TableGen/
DTargetInstrInfo.td49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
88 "mov $dst, $src", 0x88, MRMDestReg,
102 "and $dst, $src2", 0x20, MRMDestReg,
/external/swiftshader/third_party/LLVM/test/TableGen/
DTargetInstrInfo.td49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
88 "mov $dst, $src", 0x88, MRMDestReg,
102 "and $dst, $src2", 0x20, MRMDestReg,
/external/llvm/lib/Target/X86/
DX86InstrVMX.td48 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
52 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
DX86InstrShiftRotate.td691 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
697 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
703 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
708 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
713 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
719 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
728 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
735 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
742 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
749 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
[all …]
DX86InstrSystem.td120 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
123 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
139 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
142 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
170 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
172 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
174 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
DX86InstrMPX.td55 def BNDMOVMRrr : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
DX86InstrInfo.td1359 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
1361 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
1363 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
1365 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
1563 def MOV8rr_NOREX : I<0x88, MRMDestReg,
1598 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1602 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
1606 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1672 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1675 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
[all …]
DX86InstrMMX.td246 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src),
267 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
277 def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src),
DX86InstrSSE.td524 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
870 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
874 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
878 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
882 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
886 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
890 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
894 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
898 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
945 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
[all …]
DX86InstrAVX512.td575 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
782 def VEXTRACTPSZrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
2620 def rr_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
2623 def rrk_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2628 def rrkz_REV : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
2895 def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src),
2922 def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
2936 def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
2958 def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst),
2966 def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h192 MRMDestReg = 3, enumerator
472 case X86II::MRMDestReg: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp569 case X86II::MRMDestReg: in EmitVEXOpcodePrefix()
916 case X86II::MRMDestReg: in EncodeInstruction()
/external/swiftshader/third_party/LLVM/utils/TableGen/
DX86RecognizableInstr.cpp47 MRMDestReg = 3, enumerator
133 if (form == X86Local::MRMDestReg || in needsModRMForDecode()
151 if (form == X86Local::MRMDestReg || in isRegFormat()
638 case X86Local::MRMDestReg: in emitInstructionSpecifier()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h240 MRMDestReg = 3, enumerator
669 case X86II::MRMDestReg: in getMemoryOperandNo()
DX86MCCodeEmitter.cpp844 case X86II::MRMDestReg: { in EmitVEXOpcodePrefix()
1001 case X86II::MRMDestReg: in DetermineREXPrefix()
1275 case X86II::MRMDestReg: { in encodeInstruction()
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp97 MRMDestReg = 3, enumerator
148 return (form == X86Local::MRMDestReg || in isRegFormat()
604 case X86Local::MRMDestReg: in emitInstructionSpecifier()
847 case X86Local::MRMDestReg: case X86Local::MRMDestMem: in emitDecodePath()
/external/llvm/docs/TableGen/
Dindex.rst130 Format Form = MRMDestReg;
163 def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst),

12