| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 46 unsigned isLoadFromStackSlot(const MachineInstr &MI,
54 unsigned isStoreToStackSlot(const MachineInstr &MI,
109 bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst,
110 MachineInstr *&CmpInst) const override;
117 MachineInstr *IndVar, MachineInstr *Cmp,
119 SmallVectorImpl<MachineInstr *> &PrevInsts,
189 bool expandPostRAPseudo(MachineInstr &MI) const override;
192 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
206 bool isPredicated(const MachineInstr &MI) const override;
210 bool PredicateInstruction(MachineInstr &MI,
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| D | HexagonVLIWPacketizer.h | 12 std::vector<MachineInstr*> OldPacketMIs;
32 std::vector<MachineInstr*> IgnoreDepMIs;
53 bool ignorePseudoInstruction(const MachineInstr &MI,
58 bool isSoloInstruction(const MachineInstr &MI) override;
68 MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
71 bool shouldAddToPacket(const MachineInstr &MI) override;
76 bool isCallDependent(const MachineInstr* MI, SDep::Kind DepType,
78 bool promoteToDotCur(MachineInstr* MI, SDep::Kind DepType,
81 bool canPromoteToDotCur(const MachineInstr* MI, const SUnit* PacketSU,
86 bool promoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 83 bool isTriviallyReMaterializable(const MachineInstr &MI,
99 virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, in isReallyTriviallyReMaterializable()
119 virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
143 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI,
162 virtual int getSPAdjust(const MachineInstr &MI) const;
169 virtual bool isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
180 virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, in isLoadFromStackSlot()
187 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, in isLoadFromStackSlotPostFE()
198 virtual bool hasLoadFromStackSlot(const MachineInstr &MI,
207 virtual unsigned isStoreToStackSlot(const MachineInstr &MI, in isStoreToStackSlot()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetInstrInfo.h | 64 bool isTriviallyReMaterializable(const MachineInstr *MI,
79 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, in isReallyTriviallyReMaterializable()
90 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
109 virtual bool isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr()
120 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot()
128 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, in isLoadFromStackSlotPostFE()
140 virtual bool hasLoadFromStackSlot(const MachineInstr *MI, in hasLoadFromStackSlot()
151 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, in isStoreToStackSlot()
159 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, in isStoreToStackSlotPostFE()
170 virtual bool hasStoreToStackSlot(const MachineInstr *MI, in hasStoreToStackSlot()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 57 void swapOperands(MachineInstr &Inst) const;
59 void lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
60 MachineInstr &Inst) const;
62 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
63 MachineInstr &Inst, unsigned Opcode) const;
65 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
66 MachineInstr &Inst, unsigned Opcode) const;
68 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
69 MachineInstr &Inst) const;
70 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
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| D | R600InstrInfo.h | 25 class MachineInstr; variable
35 ExtractSrcs(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PV,
71 bool isTrig(const MachineInstr &MI) const;
85 bool canBeConsideredALU(const MachineInstr &MI) const;
88 bool isTransOnly(const MachineInstr &MI) const;
90 bool isVectorOnly(const MachineInstr &MI) const;
94 bool usesVertexCache(const MachineInstr &MI) const;
96 bool usesTextureCache(const MachineInstr &MI) const;
99 bool usesAddressRegister(MachineInstr &MI) const;
100 bool definesAddressRegister(MachineInstr &MI) const;
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| D | GCNHazardRecognizer.h | 24 class MachineInstr; variable
33 MachineInstr *CurrCycleInstr;
34 std::list<MachineInstr*> EmittedInstrs;
39 function_ref<bool(MachineInstr *)> IsHazardDef =
40 [](MachineInstr *) { return true; });
42 int checkSMEMSoftClauseHazards(MachineInstr *SMEM);
43 int checkSMRDHazards(MachineInstr *SMRD);
44 int checkVMEMHazards(MachineInstr* VMEM);
45 int checkDPPHazards(MachineInstr *DPP);
51 void EmitInstruction(MachineInstr *MI) override;
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 121 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { in isLeaMem()
134 inline static bool isMem(const MachineInstr &MI, unsigned Op) { in isMem()
172 SmallVectorImpl<MachineInstr *> &CondBranches,
187 int getSPAdjust(const MachineInstr &MI) const override;
195 bool isCoalescableExtInstr(const MachineInstr &MI,
199 unsigned isLoadFromStackSlot(const MachineInstr &MI,
204 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
207 unsigned isStoreToStackSlot(const MachineInstr &MI,
212 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
215 bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
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| D | X86FixupBWInsts.cpp | 85 bool getSuperRegDestIfDead(MachineInstr *OrigMI,
91 MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *MI) const;
96 MachineInstr *tryReplaceCopy(MachineInstr *MI) const;
102 MachineInstr *tryReplaceInstr(MachineInstr *MI, MachineBasicBlock &MBB,
183 bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI, in getSuperRegDestIfDead()
216 MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode, in tryReplaceLoad()
217 MachineInstr *MI) const { in tryReplaceLoad()
240 MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const { in tryReplaceCopy()
276 MachineInstr *FixupBWInstPass::tryReplaceInstr( in tryReplaceInstr()
277 MachineInstr *MI, MachineBasicBlock &MBB, in tryReplaceInstr()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.h | 42 unsigned GetInstSizeInBytes(const MachineInstr &MI) const;
44 bool isAsCheapAsAMove(const MachineInstr &MI) const override;
46 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
50 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
53 unsigned isLoadFromStackSlot(const MachineInstr &MI,
55 unsigned isStoreToStackSlot(const MachineInstr &MI,
60 bool hasShiftedReg(const MachineInstr &MI) const;
64 bool hasExtendedReg(const MachineInstr &MI) const;
67 bool isGPRZero(const MachineInstr &MI) const;
70 bool isGPRCopy(const MachineInstr &MI) const;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 55 const MachineInstr &MI, unsigned DefIdx,
68 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
84 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
95 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
107 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
108 MachineInstr &MI,
136 bool isPredicated(const MachineInstr &MI) const override;
138 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const { in getPredicate()
144 bool PredicateInstruction(MachineInstr &MI,
150 bool DefinesPredicate(MachineInstr &MI,
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.h | 109 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { in isLeaMem()
120 inline static bool isMem(const MachineInstr *MI, unsigned Op) { in isMem()
166 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
170 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
174 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
177 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
181 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
184 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
188 const MachineInstr *Orig,
201 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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| D | X86AsmPrinter.h | 52 virtual void EmitInstruction(const MachineInstr *MI);
57 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O,
59 void print_pcrel_imm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
62 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
65 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
69 void printMachineInstruction(const MachineInstr *MI);
70 void printSSECC(const MachineInstr *MI, unsigned Op, raw_ostream &O);
71 void printMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
73 void printLeaMemReference(const MachineInstr *MI, unsigned Op, raw_ostream &O,
76 void printPICLabel(const MachineInstr *MI, unsigned Op, raw_ostream &O);
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | LiveVariables.h | 95 std::vector<MachineInstr*> Kills;
102 bool removeKill(MachineInstr *MI) { in removeKill()
103 std::vector<MachineInstr*>::iterator in removeKill()
112 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
151 MachineInstr **PhysRegDef;
156 MachineInstr **PhysRegUse;
162 DenseMap<MachineInstr*, unsigned> DistanceMap;
167 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
169 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
170 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
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| D | MachineInstr.h | 43 class MachineInstr : public ilist_node<MachineInstr> {
80 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
81 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
84 friend struct ilist_traits<MachineInstr>;
90 MachineInstr(MachineFunction &, const MachineInstr &);
94 MachineInstr();
103 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
108 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
113 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
119 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveVariables.h | 89 std::vector<MachineInstr*> Kills;
94 bool removeKill(MachineInstr &MI) { in removeKill()
95 std::vector<MachineInstr *>::iterator I = in removeKill()
104 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
137 std::vector<MachineInstr *> PhysRegDef;
142 std::vector<MachineInstr *> PhysRegUse;
148 DenseMap<MachineInstr*, unsigned> DistanceMap;
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr &MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
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| D | MachineInstrBundle.h | 46 inline MachineInstr &getBundleStart(MachineInstr &MI) { in getBundleStart()
53 inline const MachineInstr &getBundleStart(const MachineInstr &MI) { in getBundleStart()
61 inline MachineBasicBlock::instr_iterator getBundleEnd(MachineInstr &MI) { in getBundleEnd()
70 getBundleEnd(const MachineInstr &MI) { in getBundleEnd()
95 MachineInstr::mop_iterator OpI, OpE;
116 explicit MachineOperandIteratorBase(MachineInstr &MI, bool WholeBundle) { in MachineOperandIteratorBase()
209 SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops = nullptr);
224 MIOperands(MachineInstr &MI) : MachineOperandIteratorBase(MI, false) {} in MIOperands()
233 ConstMIOperands(const MachineInstr &MI) in ConstMIOperands()
234 : MachineOperandIteratorBase(const_cast<MachineInstr &>(MI), false) {} in ConstMIOperands()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 42 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
72 bool isPredicated(const MachineInstr *MI) const { in isPredicated()
77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const { in getPredicate()
84 bool PredicateInstruction(MachineInstr *MI,
91 virtual bool DefinesPredicate(MachineInstr *MI,
94 virtual bool isPredicable(MachineInstr *MI) const;
98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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| D | ARMCodeEmitter.cpp | 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
85 void emitInstruction(const MachineInstr &MI);
91 void emitConstPoolInstruction(const MachineInstr &MI);
92 void emitMOVi32immInstruction(const MachineInstr &MI);
93 void emitMOVi2piecesInstruction(const MachineInstr &MI);
94 void emitLEApcrelJTInstruction(const MachineInstr &MI);
95 void emitPseudoMoveInstruction(const MachineInstr &MI);
97 void emitPseudoInstruction(const MachineInstr &MI);
98 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
104 unsigned getAddrModeSBit(const MachineInstr &MI,
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.h | 74 SmallVectorImpl<MachineInstr*> &NewMIs,
79 SmallVectorImpl<MachineInstr *> &NewMIs,
94 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
115 const MachineInstr &MI,
119 const MachineInstr &DefMI, unsigned DefIdx,
120 const MachineInstr &UseMI,
130 const MachineInstr &DefMI, in hasLowDefLatency()
146 MachineInstr &Root,
149 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
151 bool isCoalescableExtInstr(const MachineInstr &MI,
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | VirtRegMap.h | 32 class MachineInstr; variable
49 typedef std::multimap<MachineInstr*,
89 IndexedMap<MachineInstr*, VirtReg2IndexFunctor> ReMatMap;
100 std::map<MachineInstr*, std::vector<std::pair<unsigned,bool> > >
106 std::map<MachineInstr*, std::vector<unsigned> > RestorePt2VirtMap;
111 std::map<MachineInstr*, std::vector<unsigned> > EmergencySpillMap;
129 SmallVector<SmallPtrSet<MachineInstr*, 4>, 8> SpillSlotToUsesMap;
282 MachineInstr *getReMaterializedMI(unsigned virtReg) const { in getReMaterializedMI()
290 void setVirtIsReMaterialized(unsigned virtReg, MachineInstr *def) { in setVirtIsReMaterialized()
309 bool isSpillPt(MachineInstr *Pt) const { in isSpillPt()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.h | 139 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode,
141 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
143 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
145 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
147 void expandLoadStackGuard(MachineInstr *MI) const;
157 unsigned isLoadFromStackSlot(const MachineInstr &MI,
159 unsigned isStoreToStackSlot(const MachineInstr &MI,
161 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex,
171 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
173 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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| D | SystemZElimCompare.cpp | 73 Reference getRegReferences(MachineInstr &MI, unsigned Reg);
74 bool convertToBRCT(MachineInstr &MI, MachineInstr &Compare,
75 SmallVectorImpl<MachineInstr *> &CCUsers);
76 bool convertToLoadAndTest(MachineInstr &MI);
77 bool adjustCCMasksForInstr(MachineInstr &MI, MachineInstr &Compare,
78 SmallVectorImpl<MachineInstr *> &CCUsers);
79 bool optimizeCompareZero(MachineInstr &Compare,
80 SmallVectorImpl<MachineInstr *> &CCUsers);
81 bool fuseCompareOperations(MachineInstr &Compare,
82 SmallVectorImpl<MachineInstr *> &CCUsers);
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUAsmPrinter.cpp | 51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);
55 void EmitInstruction(const MachineInstr *MI) { in EmitInstruction()
63 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { in printOperand()
74 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
77 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
83 printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) in printU7ImmOperand()
91 printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) in printShufAddr()
101 printS16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) in printS16ImmOperand()
107 printU16ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) in printU16ImmOperand()
113 printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { in printMemRegReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsAsmPrinter.h | 24 class MachineInstr; variable
42 void EmitInstruction(const MachineInstr *MI);
52 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
55 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
58 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
59 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
60 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
61 void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O);
62 void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
65 virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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